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LMKDB1104FS85 Scheda tecnica(PDF) 4 Page - Texas Instruments

Il numero della parte LMKDB1104FS85
Spiegazioni elettronici  LMKDB12xx PCIe Gen 1 to Gen 7 Ultra Low Jitter 2 Input Clock MUX
PDF  69 Pages
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Produttore elettronici  TI2 [Texas Instruments]
Homepage  https://www.ti.com
Logo TI2 - Texas Instruments

LMKDB1104FS85 Scheda tecnica(HTML) 4 Page - Texas Instruments

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5 Pin Configuration and Functions
1
vZOUT_SEL
36
^vSADR1_tri
2
VDD_DIG
35
^OE2#
3
^PWRGD/PWRDN#
34
^OE3#/SBI_CLK
4
CLKIN0_P
33
CLK3_N
5
CLKIN0_N
32
CLK3_P
6
VDD_IN0
31
VDDA
7
^vSADR0_tri
30
VDDO_BANK0
8
CLKIN1_P
29
LOS#
9
CLKIN1_N
28
VDDO_BANK1
10
SMB_DATA
27
CLK4_N
11
SMB_CLK
26
CLK4_P
12
VDD_IN1
25
^OE4#/SBI_IN
Not to scale
Thermal Pad (GND)
Figure 5-1. LMKDB1208 6mm × 6mm VQFN Package 48 Pin Top View
Legend
CLOCK INPUTS
CLOCK OUTPUTS
POWER
GND
LOGIC CONTROLS / STATUS
NO CONNECT
Table 5-1. LMKDB1208 Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME(2) (3)
NO.
CLOCK INPUTS
CLKIN0_P
4
I
Differential clock input 0.
CLKIN0_N
5
I
CLKIN1_P
8
I
Differential clock input 1.
CLKIN1_N
9
I
CLOCK OUTPUTS
CLK0_P
45
O
LP-HCSL differential clock output 0. No connect if unused.
CLK0_N
46
O
CLK1_P
40
O
LP-HCSL differential clock output 1. No connect if unused.
CLK1_N
41
O
CLK2_P
37
O
LP-HCSL differential clock output 2. No connect if unused.
CLK2_N
38
O
CLK3_P
32
O
LP-HCSL differential clock output 3. No connect if unused.
CLK3_N
33
O
LMKDB1202, LMKDB1204, LMKDB1208
SNAS927A – AUGUST 2025 – REVISED APRIL 2026
www.ti.com
4
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Copyright © 2026 Texas Instruments Incorporated
Product Folder Links: LMKDB1202 LMKDB1204 LMKDB1208



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