LMKDB1104FS85 datasheet(49/69 Pages) TI2

49 / 69 page

Table 9-47. R91 Register Field Descriptions

Bit

Field

Type

Reset

Description

7:4

SLEWRATE_OPT

R/W

There are four register assignments each storing a slew rate value

(chosen out of the 16 available slew rate values). This register bits

relate to the 2nd option. Go to Programmable Output Slew Rate

section for more information.

0h = 0 (fastest)

1h = 1

2h = 2

3h = 3

4h = 4

5h = 5

6h = 6 (Default for LMKDB1208)

7h = 7

8h = 8

9h = 9

Ah = 10

Bh = 11

Ch = 12

Dh = 13

Eh = 14

Fh = 15 (slowest)

3:0

RESERVED

Reserved bits

10 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

10.1 Application Information

The LMKDB12xx devices are a family of ultra-low additive jitter LP-HCSL clock mux. The device can be

controlled through SMBus registers, Side Band Interface, and OE# pins.

10.2 Typical Application

This example shows PCIe and Ethernet clock distribution. Provide multiple copies of PCIe clocks (100MHz) or

Ethernet clocks (156.25MHz) based on the given source.

PCIe Clock Source #1

LMKDB family

PCIe Clock Buffer or MUX

SMBus

Control

OE#

Control

PCIe PHY

LP-HCSL

PCIe PHY

PCIe Device

Side-Band

Interface

Control Interface

PCIe Clock Source #2

MUX only, optional

Figure 10-1. Typical Application

www.ti.com

LMKDB1202, LMKDB1204, LMKDB1208

SNAS927A – AUGUST 2025 – REVISED APRIL 2026

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