LMKDB1104FS85 datasheet(46/69 Pages) TI2

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Table 9-40. R17 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

3:0

AMP_0

R/W

BANK0 Differential output Control = 0.6V to approximately 1V

25mV/step Default = 0.75V

0h = 600mV

1h = 625mV

2h = 650mV

3h = 675mV

4h = 700mV

5h = 725mV

6h = 750mV

7h = 775mV

8h = 800mV

9h = 825mV

Ah = 850mV

Bh = 875mV

Ch = 900mV

Dh = 925mV

Eh = 950mV

Fh = 975mV

9.2.16 R18 Register (Offset = 12h) [Reset = 0Ch]

R18 is shown in Table 9-41.

Return to the Summary Table.

Table 9-41. R18 Register Field Descriptions

Bit

Field

Type

Reset

Description

7:4

RESERVED

Reserved bits

PD_RESTOREB

R/W

Save Configuration in Power Down

1'b0 : config cleared

1'b1: config saved

SDATA_TIMEOUT_EN

R/W

Enable SMB SDATA time out monitoring

1'b0 : disable SDATA time out

1'b1: enable SDATA time out

LOS1b_RB

Real time read back of loss detect block output

0h = LOS event detected

1h = NO LOS event detected

LOS0b_RB

Real time read back of loss detect block output

0h = LOS event detected

1h = NO LOS event detected

9.2.17 R20 Register (Offset = 14h) [Reset = 00h]

R20 is shown in Table 9-42.

Return to the Summary Table.

Table 9-42. R20 Register Field Descriptions

Bit

Field

Type

Reset

Description

CLK_IMPEDANCE_3

R/W

Output clock impedance select

0h = 85Ω

1h = 100Ω

6:5

RESERVED

Reserved bits

CLK_IMPEDANCE_2

R/W

Output clock impedance select

0h = 85Ω

1h = 100Ω

LMKDB1202, LMKDB1204, LMKDB1208

SNAS927A – AUGUST 2025 – REVISED APRIL 2026

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