H8SSLASH2218 datasheet(36/750 Pages) RENESAS

36 / 750 page

Rev.6.00 Jun. 03, 2008 Page xxxiv of xlvi

REJ09B0074-0600

Figure 12.4 Example of Average Transfer Rate Setting when TPU Clock Is Input (4) ............394

Figure 12.5 Data Format in Asynchronous Communication

(Example with 8-Bit Data, Parity, Two Stop Bits) .................................................403

Figure 12.6 Receive Data Sampling Timing in Asynchronous Mode........................................405

Figure 12.7 Relationship between Output Clock and Transfer Data Phase

(Asynchronous Mode) ............................................................................................406

Figure 12.8 Sample SCI Initialization Flowchart.......................................................................407

Figure 12.9 Example of Operation in Transmission in Asynchronous Mode

(Example with 8-Bit Data, Parity, One Stop Bit) ...................................................408

Figure 12.10 Sample Serial Data Transmission Flowchart ..........................................................409

Figure 12.11 Example of SCI Operation in Reception

(Example with 8-Bit Data, Parity, One Stop Bit) ...................................................410

Figure 12.12 Sample Serial Data Reception Flowchart (1)..........................................................411

Figure 12.12 Sample Serial Data Reception Flowchart (2)..........................................................412

Figure 12.13 Example of Communication Using Multiprocessor Format

(Transmission of Data H'AA to Receiving Station A)............................................414

Figure 12.14 Sample Multiprocessor Serial Data Transmission Flowchart .................................415

Figure 12.15 Example of SCI Operation in Reception

(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) ...............................416

Figure 12.16 Sample Multiprocessor Serial Data Reception Flowchart (1).................................417

Figure 12.16 Sample Multiprocessor Serial Data Reception Flowchart (2).................................418

Figure 12.17 Data Format in Synchronous Communication (For LSB-First)..............................419

Figure 12.18 Sample SCI Initialization Flowchart.......................................................................420

Figure 12.19 Sample SCI Transmission Operation in Clocked Synchronous Mode....................422

Figure 12.20 Sample Serial Data Transmission Flowchart ..........................................................423

Figure 12.21 Example of SCI Operation in Reception ................................................................424

Figure 12.22 Sample Serial Data Reception Flowchart ...............................................................425

Figure 12.23 Sample Flowchart of Simultaneous Serial Data Transmit

and Receive Operations ..........................................................................................426

Figure 12.24 Schematic Diagram of Smart Card Interface Pin Connections ...............................427

Figure 12.25 Normal Smart Card Interface Data Format.............................................................428

Figure 12.26 Direct Convention (SDIR = SINV = O/

E = 0)........................................................428

Figure 12.27 Inverse Convention (SDIR = SINV = O/

E = 1)......................................................429

Figure 12.28 Receive Data Sampling Timing in Smart Card Mode

(Using Clock of 372 Times the Transfer Rate).......................................................430

Figure 12.29 Retransfer Operation in SCI Transmit Mode ..........................................................433

Figure 12.30 TEND Flag Generation Timing in Transmission Operation ...................................433

Figure 12.31 Example of Transmission Processing Flow ...........................................................434

Figure 12.32 Retransfer Operation in SCI Receive Mode ...........................................................435

Figure 12.33 Example of Reception Processing Flow .................................................................436

Figure 12.34 Timing for Fixing Clock Output Level ...................................................................436

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