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H8S/2218 Scheda tecnica(PDF) 72 Page - Renesas Technology Corp |
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H8S/2218 Scheda tecnica(HTML) 72 Page - Renesas Technology Corp |
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72 / 750 page ![]() Section 1 Overview Rev.6.00 Jun. 03, 2008 Page 24 of 698 REJ09B0074-0600 Pin No. Type Symbol TFP-100G, TFP-100GV BP-112, BP-112V FP-64E, FP-64EV, TNP-64B, TNP-64BV I/O Function Data bus D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 B9 D8 A10 B10 B11 C10 D9 C11 D10 E8 D11 E9 E10 E11 F8 F10 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ I/O These pins constitute a bi- directional data bus. (Supported only by the H8S/2218 Group) Bus control CS5 CS4 CS3 CS2 CS1 CS0 56 63 25 26 27 28 H10 F11 J2 K2 L2 H4 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Output Signals for selecting areas 5 to 0 in the external address space. (Supported only by the H8S/2218 Group) AS 91 D6 ⎯ Output When this pin is low, it indicates that address output on the address bus is enabled. (Supported only by the H8S/2218 Group) RD 92 A5 ⎯ Output When this pin is low, it indicates that the external address space can be read. (Supported only by the H8S/2218 Group) |
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