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H8S/2218 Scheda tecnica(PDF) 99 Page - Renesas Technology Corp |
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H8S/2218 Scheda tecnica(HTML) 99 Page - Renesas Technology Corp |
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99 / 750 page ![]() Section 2 CPU Rev.6.00 Jun. 03, 2008 Page 51 of 698 REJ09B0074-0600 Table 2.6 Shift Instructions Instruction Size* Function SHAL SHAR B/W/L Rd (shift) → Rd Performs an arithmetic shift on general register contents. 1-bit or 2 bit shift is possible. SHLL SHLR B/W/L Rd (shift) → Rd Performs an logical shift on general register contents. 1-bit or 2 bit shift is possible. ROTL ROTR B/W/L Rd (rotate) → Rd Rotates general register contents. 1-bit or 2 bit rotation is possible. ROTXL ROTXR B/W/L Rd (rotate) → Rd Rotates general register contents through the carry flag. 1-bit or 2 bit rotation is possible. Note: * Size refers to the operand size. B: Byte W: Word L: Longword |
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