H8SSLASH2218 datasheet(46/750 Pages) RENESAS

46 / 750 page

Rev.6.00 Jun. 03, 2008 Page xliv of xlvi

REJ09B0074-0600

Table 12.9

Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode).............402

Table 12.10 Serial Transfer Formats (Asynchronous Mode)......................................................404

Table 12.11 SSR Status Flags and Receive Data Handling ........................................................411

Table 12.12 SCI Interrupt Sources .............................................................................................440

Table 12.13 Interrupt Sources in Smart Card Interface Mode ....................................................441

Section 13 Boundary Scan Function

Table 13.1

Pin Configuration....................................................................................................451

Table 13.2

Instruction Configuration........................................................................................452

Table 13.3

IDCODE Register Configuration............................................................................454

Table 13.4

Correspondence between LSI Pins and Boundary Scan Register ...........................455

Section 14 Universal Serial Bus (USB)

Table 14.1

Pin Configuration....................................................................................................467

Table 14.2

Relationship between UTSTR0 Setting and Pin Output .........................................490

Table 14.3

Relationship between Pin Input and UTSTR1 Monitoring Value ..........................491

Table 14.4

Interrupt Sources.....................................................................................................495

Table 14.5

Command Decoding by Firmware..........................................................................516

Section 15 A/D Converter

Table 15.1

Pin Configuration....................................................................................................537

Table 15.2

Analog Input Channels and Corresponding ADDR Registers ................................538

Table 15.3

A/D Conversion Time (Single Mode).....................................................................545

Table 15.4

A/D Conversion Time (Scan Mode) .......................................................................545

Table 15.5

A/D Converter Interrupt Source..............................................................................546

Table 15.6

Analog Pin Specifications.......................................................................................549

Section 17 Flash Memory (F-ZTAT Version)

Table 17.1

Differences between Boot Mode and User Program Mode ....................................555

Table 17.2

Pin Configuration....................................................................................................560

Table 17.3

Setting On-Board Programming Modes .................................................................567

Table 17.4

Boot Mode Operation .............................................................................................570

Table 17.5

System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate Is

Possible...................................................................................................................570

Table 17.6

Enumeration Information........................................................................................571

Table 17.7

USB Boot Mode Operation.....................................................................................574

Table 17.8

Flash Memory Operating States..............................................................................586

Table 17.9

Registers Present in F-ZTAT Version but Absent in Masked ROM Version .........592

Section 19 Clock Pulse Generator

Table 19.1

Damping Resistance Value .....................................................................................600

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