H8SSLASH2218 datasheet(411/750 Pages) RENESAS

411 / 750 page

Section 12 Serial Communication Interface

Rev.6.00 Jun. 03, 2008 Page 363 of 698

REJ09B0074-0600

Section 12 Serial Communication Interface

This LSI has two independent serial communication interface (SCI) channels. The SCI can handle

both asynchronous and clocked synchronous serial communication. Asynchronous serial data

communication can be carried out using standard asynchronous communication chips such as a

Universal Asynchronous Receiver/Transmitter (UART) or an Asynchronous Communication

Interface Adapter (ACIA). A function is also provided for serial communication between

processors (multiprocessor communication function). The SCI also supports the smart card (IC

card) interface based on ISO/IEC 7816-3 (Identification Card) as an enhanced asynchronous

communication function.

12.1

Features

• Choice of asynchronous or clocked synchronous serial communication mode

• Full-duplex communication capability

The transmitter and receiver are mutually independent, enabling transmission and reception to

be executed simultaneously.

Double-buffering is used in both the transmitter and the receiver, enabling continuous

transmission and continuous reception of serial data.

On-chip baud rate generator allows any bit rate to be selected

External clock can be selected as a transfer clock source (except for in Smart Card interface

mode).

• Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data)

• Four interrupt sources

Transmit-end, transmit-data-empty, receive-data-full, and receive error — that can issue

requests.

The transmit-data-empty interrupt and receive data full interrupts can be used to activate the

direct memory access controller (DMAC).

• Module stop mode can be set

Asynchronous Mode

• Data length: 7 or 8 bits

• Stop bit length: 1 or 2 bits

• Parity: Even, odd, or none

• Receive error detection: Parity, overrun, and framing errors

• Break detection: Break can be detected by reading the RxD pin level directly in the case of a

framing error

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