H8SSLASH2218 datasheet(431/750 Pages) RENESAS

431 / 750 page

Section 12 Serial Communication Interface

Rev.6.00 Jun. 03, 2008 Page 383 of 698

REJ09B0074-0600

Bit

Bit Name Initial Value R/W

Description

MPB

Multiprocessor Bit

This bit is not used in Smart Card interface mode.

MPBT

R/W

Multiprocessor Bit Transfer

Write 0 to this bit in Smart Card interface mode.

Note:* The write value should always be 0 to clear the flag.

12.3.8

Smart Card Mode Register (SCMR)

SCMR is a register that selects the transfer format. In this LSI, Smart Card interface mode cannot

be specified.

Bit

Bit Name Initial Value

R/W

Description

7 to 4 —

All 1

—

Reserved

These bits are always read as 1.

DIR

R/W

Data Transfer Direction

Selects the serial/parallel conversion format.

0: LSB-first in transfer

1: MSB-first in transfer

The bit setting is valid only when the transfer data format

is 8 bits.

INV

R/W

Data Invert

Specifies inversion of the data logic level. The SINV bit

does not affect the logic level of the parity bit. To invert

the parity bit, invert the O/

E bit in SMR.

0: TDR contents are transmitted as they are. Receive

data is stored as it is in RDR

1: TDR contents are inverted before being transmitted.

Receive data is stored in inverted form in RDR

—

Reserved

This bit is always read as 1.

SMIF

R/W

Smart Card Interface Mode Select

When this bit is set to 1, smart card interface mode is

selected.

0: Normal asynchronous or clocked synchronous mode

1: Smart card interface mode

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