H8SSLASH2218 datasheet(443/750 Pages) RENESAS

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Section 12 Serial Communication Interface

Rev.6.00 Jun. 03, 2008 Page 395 of 698

REJ09B0074-0600

12.3.11

Bit Rate Register (BRR)

BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control

independently for each channel, different bit rates can be set for each channel. Table 12.2 shows

the relationships between the N setting in BRR and bit rate B for normal asynchronous mode,

clocked synchronous mode, and Smart Card interface mode. The initial value of BRR is H'FF, and

it can be read from or written to by the CPU at all times.

Table 12.2

Relationships between the N Setting in BRR and Bit Rate B

Mode

ABCS

Bit Rate

Error

B =

× 22n-1 × (N + 1)

φ × 106

Error (%) =

– 1

× 100

× 64 × 22n-1 × (N + 1)

φ × 106

Asynchronous

mode

B =

× 22n-1 × (N + 1)

φ × 106

Error (%) =

– 1

× 100

× 32 × 22n-1 × (N + 1)

φ × 106

Clocked

synchronous

mode

B =

× 22n-1 × (N + 1)

φ × 106

⎯

Smart Card

interface mode

B =

× 22n+1 × (N + 1)

φ × 106

Error (%) =

– 1

× 100

× S × 22n+1 × (N + 1)

φ × 106

Legend:

Bit rate (bps)

BRR setting for baud rate generator (0

≤ N ≤ 255)

φ:

Operating frequency (MHz)

n, S: Determined by the SMR settings shown in the following tables.

×:

Don’t care

SMR Setting

CKS1

CKS0

Clock Source

BCP1

BCP0

φ/4

φ/16

372

φ/64

256

Table 12.3 shows sample N settings in BRR in normal asynchronous mode. Table 12.4 shows the

maximum bit rate for each frequency in normal asynchronous mode. Table 12.6 shows sample N

settings in BRR in clocked synchronous mode. Table 12.8 shows sample N settings in BRR in

Smart Card interface mode. In Smart Card interface mode, S (the number of basic clock periods in

a 1-bit transfer interval) can be selected. For details, see section 12.7.5, Receive Data Sampling

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