H8SSLASH2218 datasheet(453/750 Pages) RENESAS

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Section 12 Serial Communication Interface

Rev.6.00 Jun. 03, 2008 Page 405 of 698

REJ09B0074-0600

12.4.2

Receive Data Sampling Timing and Reception Margin in Asynchronous Mode

In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times* the

transfer rate. In reception, the SCI samples the falling edge of the start bit using the basic clock,

and performs internal synchronization. Receive data is latched internally at the rising edge of the

8th* pulse of the basic clock as shown in Figure 12.6. Thus, the reception margin in asynchronous

mode is given by formula (1) below.

M = | (0.5 –

) – (L – 0.5) F –

(1+ F) |

× 100 [%]

... Formula (1)

| D – 0.5 |

Where M: Reception margin

N: Ratio of bit rate to clock (N = 16 if ABCS = 0, N = 8 if ABCS = 1)

D: Clock duty (D = 0 to 1.0)

L: Frame length (L = 9 to 12)

F: Absolute value of clock rate deviation

Assuming values of F (absolute value of clock rate deviation) = 0, D (clock duty) = 0.5, and N

(ratio of bit rate to clock) = 16 in formula (1), the reception margin can be given by the formula.

M = {0.5 – 1/(2

× 16)} × 100 [%] = 46.875%

However, this is only the computed value, and a margin of 20% to 30% should be allowed for in

system design.

Internal basic

clock

16 clocks *

8 clocks *

Receive data

(RxD)

Synchronization

sampling timing

Start bit

Data sampling

timing

15 0

Figure 12.6 Receive Data Sampling Timing in Asynchronous Mode

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