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H8S/2218 Scheda tecnica(PDF) 484 Page - Renesas Technology Corp

Il numero della parte H8S/2218
Spiegazioni elettronici  16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series
PDF  750 Pages
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8S/2218 Scheda tecnica(HTML) 484 Page - Renesas Technology Corp

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Section 12 Serial Communication Interface
Rev.6.00 Jun. 03, 2008 Page 436 of 698
REJ09B0074-0600
Initialization
Read RDR and clear
RDRF flag in SSR to 0
Clear RE bit to 0
Start reception
Start
Error processing
No
No
No
Yes
Yes
ORER = 0 and
PER = 0
RDRF = 1?
All data received?
Yes
Figure 12.33 Example of Reception Processing Flow
12.7.9
Clock Output Control
When the GM bit in SMR is set to 1, the clock output level can be fixed with bits CKE0 and CKE1
in SCR. At this time, the minimum clock pulse width can be made the specified width. Figure
12.34 shows the timing for fixing the clock output level. In this example, GM is set to 1, CKE1 is
cleared to 0, and the CKE0 bit is controlled.
Specified pulse width
SCK
CKE0
Specified pulse width
Figure 12.34 Timing for Fixing Clock Output Level



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