H8SSLASH2218 datasheet(518/750 Pages) RENESAS

518 / 750 page

Section 14 Universal Serial Bus (USB)

Rev.6.00 Jun. 03, 2008 Page 470 of 698

REJ09B0074-0600

Bit

Bit Name

Initial Value

R/W

Description

UIFRST

R/W

USB Interface Software Reset

Controls USB module internal reset. When the

UIFRST bit is set to 1, the USB internal modules other

than UCTLR, UIER3, and the CK48READY bit in

UIFR3 are all reset. At initialization, the UIFRST bit

must be cleared to 0 after the USB operating clock (48

MHz) stabilization time has passed following the

clearing of the USB module stop 2 bit.

0: Sets the USB internal modules to the operating

state. (At initialization, this bit must be cleared after

the USB operating clock stabilization time has

passed.)

1: Sets the USB internal modules other than UCTLR,

UIER3, and the CK48READY bit in UIFR3 to the

reset state.

If the UIFRST bit is set to 1 after it is cleared to 0, the

UDCRST bit should also be set to 1 simultaneously.

UDCRST

R/W

UDC Core Software Reset

Controls reset of the UDC core in the USB module.

When the UDCRST bit is set to 1, the UDC core is

reset and the USB bus synchronization operation

stops. At initialization, UDCRST must be cleared to 0

after D+ pull-up by the port (P36) control following the

clearing of the UIFRST bit. In the suspend state, to

maintain the internal state of the UDC core, enter

power-down mode after setting the USB module stop

2 bit with the UDCRST bit to be maintained to 0. After

VBUS disconnection detection, UDCRST must be set

to 1.

0: Sets the UDC core in the USB module to operating

state. (At initialization, UDCRST must be cleared

to 0 after D+ pull-up by the port control following

the clearing of the UIFRST bit.)

1: Sets the UDC core in the USB module to reset

state. (In the suspend state, UDCRST must not be

set to 1; after VBUS disconnection detection,

UDCRST must be set to 1.)

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