H8SSLASH2218 datasheet(571/750 Pages) RENESAS

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Section 14 Universal Serial Bus (USB)

Rev.6.00 Jun. 03, 2008 Page 523 of 698

REJ09B0074-0600

(3) EP0, EP1, or EP3 DMA Transfer

(a) EPnPKTE Bits of UTRG0 (n = 0i, 1, or 3)

Note that 1 is not automatically written to EPnPKTE in case of auto-request transfer. Always write

1 to EPnPKTE by the CPU. The following example shows when 150-byte data is transmitted from

EP1 to the host. In this case, 1 should be written to EP2PKTE three times as shown in figure

14.24.

(b) EP1 DMA Transfer Procedure

The DMAC transfer unit should be one packet. Therefore, set the number of transfers so that it is

equal to or less than the maximum packet size of each endpoint.

1. Confirm that UIFR1/EP1EMPTY flag is 1.

2. DMAC settings for EP1 data transfer (such as auto-request and address setting).

3. Set the number of transfers for 64 bytes (the maximum packet size or less) in the DMAC.

4. Activate the DMAC (write 1 to DTE after reading DTE as 0).

5. DMA transfer.

6. Write 1 to the UTRG0/EP1PKTE bit after the DMA transfer is completed.

7. Repeat steps 1 to 6 above.

8. Confirm that UIFR1/EP1EMPTY flag is 1.

9. Set the number of transfer for 22 bytes in the DMAC.

10. Activate the DMAC (write 1 to DTE after reading DTE as 0).

11. DMA transfer.

12. Write 1 to the UTRG0/EP1PKTE bit after the DMA transfer is completed.

Write 1 to

EP1PKTE

Write 1 to

EP1PKTE

Write 1 to

EP1PKTE

64 bytes

22 bytes

Figure 14.24 EP1PKTE Operation in UTRG0 (Auto-Request)

(4) EP0o or EP2 DMA Transfer

(a) EPnRDFN Bits of UTRG0 (n = 0o or 2)

Note that 1 is not automatically written to EPnRDFN in case of auto-request transfer. Always write

1 to EPnRDFN by the CPU. The following example shows when EP2 receives 150-byte data from

the host. In this case, 1 should be written to EP2RDFN three times as shown in figure 14.25.

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