H8SSLASH2218 datasheet(743/750 Pages) RENESAS

743 / 750 page

Index

Rev.6.00 Jun. 03, 2008 Page 695 of 698

REJ09B0074-0600

Index

16-Bit Timer Pulse Unit.......................... 273

A/D Conversion Time............................. 544

A/D Converter ........................................ 535

A/D Converter Activation....................... 323

Absolute Address...................................... 59

Address Space........................................... 38

Addressing Mode...................................... 58

ADI ......................................................... 546

Advanced Mode........................................ 36

Arithmetic Operations Instructions........... 49

Asynchronous Mode ............................... 403

Bcc ...................................................... 46, 54

Bit Manipulation Instructions ................... 52

Bit rate .................................................... 395

Block Data Transfer Instruction................ 56

Boot Mode .............................................. 567

Boundary Scan........................................ 449

Branch Instructions ................................... 54

Break....................................................... 441

Buffer Operation ..................................... 309

Bulk-In Transfer ..................................... 513

Bulk-Out Transfer................................... 515

Bus Arbitration ....................................... 155

Bus cycle................................................. 133

Clock Pulse Generator ............................ 595

Condition Field ......................................... 57

Condition-Code Register .......................... 42

Control Transfer...................................... 506

CPU Operating Modes.............................. 34

Data reading procedure ........................... 359

Data Transfer Instructions ........................ 48

DMA Transfer Specifications ................. 520

Effective Address................................ 58, 62

Effective Address Extension..................... 57

Emulation................................................ 577

Erase/Erase-Verify.................................. 581

Erasing units ................................... 558, 559

Error Protection....................................... 583

Exception Handling .................................. 81

Extended Control Register (EXR) ............ 41

External Trigger ...................................... 545

Flash Memory ......................................... 553

Framing error .......................................... 410

Free-running count operation.................. 302

General Registers ...................................... 40

Hardware Protection ............................... 583

Immediate ................................................. 60

Input Capture Function ........................... 305

Instruction Set ........................................... 45

Internal bus masters ................................ 115

Interrupt Control Mode ........................... 103

Interrupt Controller ................................... 91

Interrupt Exception Handling Vector Table

............................................................ 101

Interrupt Mask Bit..................................... 42

Interrupt mask level .................................. 41

Interrupt priority register........................... 91

Interrupt-In Transfer ............................... 512

Interrupts................................................... 87

Interval Timer Mode ............................... 344

Logic Operations Instructions................... 50

Mark State............................................... 442

Masked ROM.......................................... 593

Memory cycle ......................................... 131

Memory Indirect ....................................... 61

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