7733 datasheet(363/940 Pages) RENESAS

363 / 940 page

represents that bits 0 to 2 and bits 4 to 7 are not used for software reset.

functions as a

output pin.)

RESET

7733 Group User’s Manual

13–12

Bit

Bit name

Functions

At reset

Processor mode bits

Wait bit

Software reset bit

Must be fixed to “0.”

Clock

output selection bit

(Note 2)

0 0: Single-chip mode

0 1: Memory expansion mode

1 0: Microprocessor mode

1 1: Do not select.

0: Software wait is inserted when

accessing external area.

1: No software wait is inserted

when accessing external area.

Microcomputer is reset by

setting this bit to “1.”

This bit is “0” at reading.

0 0: 7 cycles of

0 1: 4 cycles of

1 0: 2 cycles of

1 1: Do not select.

0: Clock

output is disabled.

(P4

programmable I/O port.)

1: Clock

output is enabled.

(Port P4 2 functions as a clock

b1 b0

b5 b4

Processor mode register 0 (address 5E 16)

(Note 1)

Notes 1:

When the Vcc-level voltage is applied to pin CNVss, this bit is set to “1” after reset.

(At reading, this bit is always “1.”)

This bit is ignored in the microprocessor mode. (It may be “0” or “1.”)

Interrupt priority detection

time selection bits

13.2 Software reset

When the power source voltage satisfies the recommended operating conditions and the main clock is stably

supplied (Note), the microcomputer is reset by writing “1” to the software reset bit (bit 3 at address 5E16).

(This is called “Software reset.”) In this case, the microcomputer initializes pins, CPU, and SFR area as in

the case of a hardware reset. However, the microcomputer retains the contents of the internal RAM area.

(Refer to Table 13.1.1 and Figures 13.1.2. to 13.1.6.)

After completing initialization, the microcomputer performs “internal processing sequence after reset.” (Refer

to Figure 13.1.7.) Then, a program is executed beginning with the address set in the reset vector addresses

(addresses FFFE16 and FFFF16).

Note: This means “when a oscillator is stably oscillating or when an external clock is stably input from pin

XIN.” For clocks, refer to chapter “14. CLOCK GENERATING CIRCUIT.”

Fig. 13.2.1 Structure of processor mode register 0

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