7733 datasheet(47/940 Pages) RENESAS

47 / 940 page

CENTRAL PROCESSING UNIT (CPU)

7733 Group User’s Manual

2.1 Central processing unit

2–8

2.1.9 Processor status register (PS)

The processor status register consists of 11 bits.

Figure 2.1.5 shows the structure of the processor status register.

b15

b14

b10

b11

b12

b13

Processor status register (PS)

IPL

Note: “0” is always read from bits 11 to 15.

Fig. 2.1.5 Structure of processor status register

(1) Bit 0: Carry flag (C)

This flag retains a carry or borrow which occur in the Arithmetic Logic unit (ALU) during an arithmetic

or logic operation. This flag is also affected by a shift or rotate instruction. When the BCC or BCS

instruction is executed, the program branches according to this flag’s state. When setting this flag to

“1,” execute the SEC or SEP instruction; when clearing this flag to “0,” execute the CLC or CLP

instruction.

(2) Bit 1: Zero flag (Z)

This flag is set to “1” when the result of an arithmetic operation or data transfer is “0” and cleared to

“0” when otherwise. When the BNE or BEQ instruction is executed, the program branches according

to this flag’s state. This flag is ignored for an addition and subtraction instructions (the ADC and the

SBC instructions) in the decimal mode. When setting this flag to “1,” execute the SEP instruction;

when clearing this flag to “0,” execute the CLP instruction.

(3) Bit 2: Interrupt disable flag (I)

This flag disables all maskable interrupts, in other words interrupts other than watchdog timer, the

BRK instruction, and zero division interrupts. Interrupts are disabled when this flag is “1.” When an

interrupt request is accepted, this flag is automatically set to “1” and disables multiple interrupts. When

setting this flag to “1,” execute the SEI or SEP instruction; when clearing this flag to “0,” execute the

CLI or CLP instruction.

At reset, this flag is set to “1.”

(4) Bit 3: Decimal mode flag (D)

This flag determines whether addition and subtraction are performed in binary or decimal.

Binary arithmetic is performed when this flag is “0.”

When it is “1,” decimal arithmetic is performed. At this time, each word is processed as 2- or 4-digit

decimal data. (The digit’s number is determined by the data length flag (m)).

Decimal adjust is automatically performed. (Note that a decimal operation is enabled only in execution

of the ADC or SBC instruction.)

When setting this flag to “1,” execute the SEP instruction; when clearing this flag to “0,” execute the

CLP instruction.

At reset, this flag is cleared to “0.”

7733 Scheda tecnica(PDF) 47 Page - Renesas Technology Corp

7733 Scheda tecnica(HTML) 47 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL