7733 datasheet(8/940 Pages) RENESAS

8 / 940 page

7733 Group User’s Manual

Table of contents

PART 1 7733 Group

CHAPTER 1. OVERVIEW

1.1 Performance overview ........................................................................................................... 1-3

1.2 Pin configuration.................................................................................................................... 1-4

1.3 Pin description ....................................................................................................................... 1-5

1.3.1 Examples of handling unused pins .............................................................................. 1-8

1.4 Block diagram ....................................................................................................................... 1-11

CHAPTER 2. CENTRAL PROCESSING UNIT (CPU)

2.1 Central processing unit ........................................................................................................ 2-2

2.1.1 Accumulator (Acc) .......................................................................................................... 2-3

2.1.2 Index register X (X) ........................................................................................................ 2-3

2.1.3 Index register Y (Y) ........................................................................................................ 2-3

2.1.4 Stack pointer (S) ............................................................................................................. 2-4

2.1.5 Program counter (PC) .................................................................................................... 2-5

2.1.6 Program bank register (PG) .......................................................................................... 2-5

2.1.7 Data bank register (DT) ................................................................................................. 2-6

2.1.8 Direct page register (DPR) ............................................................................................ 2-6

2.1.9 Processor status register (PS) ...................................................................................... 2-8

2.2 Bus interface unit ................................................................................................................ 2-10

2.2.1 Overview ........................................................................................................................ 2-10

2.2.2 Functions of bus interface unit (BIU) ........................................................................ 2-12

2.2.3 Operation of bus interface unit (BIU) ........................................................................ 2-14

2.3 Accessible area .................................................................................................................... 2-16

2.3.1 Banks ............................................................................................................................. 2-17

2.3.2 Direct page .................................................................................................................... 2-17

2.4 Memory allocation ................................................................................................................ 2-18

2.4.1 Memory allocation in internal area .............................................................................2-18

2.5 Processor modes ................................................................................................................. 2-24

2.5.1 Single-chip mode .......................................................................................................... 2-25

2.5.2 Memory expansion and Microprocessor modes ....................................................... 2-25

2.5.3 Setting of processor modes ........................................................................................ 2-28

CHAPTER 3. PROGRAMMABLE I/O PORTS

3.1 Programmable I/O ports ....................................................................................................... 3-2

3.1.1 Port Pi direction register ................................................................................................ 3-3

3.1.2 Port Pi register ................................................................................................................ 3-4

3.2 Port peripheral circuits ......................................................................................................... 3-6

3.3 Pull-up function ...................................................................................................................... 3-8

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3.3.1 Pull-up function for ports P54 to P57 (KI0 to KI3) ...................................................... 3-8

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3.3.2 Pull-up function for ports P62 to P64 (INT0 to INT2) ................................................. 3-8

3.4 Internal peripheral devices’ I/O functions (Ports P42 and P5 to P8) ...................... 3-10

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