7733 datasheet(95/940 Pages) RENESAS

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7733 Group User's Manual

INTERRUPTS

4–16

Pushed in 3 times

Pushes 16 bits at a time.

(1) When stack pointer (S)’s contents is even

Processor status register’s low-order byte (PS L )

Processor status register’s high-order byte (PS H )

Program counter’s low-order byte (PC L )

Program counter’s high-order byte (PC H )

Program bank register (PG)

Address

S–4 (even)

S–3 (odd)

S–2 (even)

S–1 (odd)

S (even)

Order for push

S–5 (odd)

Processor status register’s low-order byte (PS L )

Processor status register’s high-order byte (PS H )

Program counter’s low-order byte (PC L)

Program counter’s high-order byte (PC H )

Program bank register (PG)

Address

S–4 (odd)

S–3 (even)

S–2 (odd)

S–1 (even)

S (odd)

(2) Stack Pointer (S)’s contents is odd

Pushes by the 8 bits.

Order for push

Pushed in 5 times

S–5 (even)

g “S” is the initial address that the stack pointer (S) indicates when an interrupt request is accepted.

S’s contents is “S–5” after the above registers are pushed.

4.7.2 How to push registers

The way to push registers depends on whether the stack pointer (S)’s contents at interrupt request acceptance

is even or odd.

When the stack pointer (S)’s contents is even, each of the program counter (PC)’s contents and processor

status register (PS)’s contents is simultaneously pushed by the 16 bits. When the stack pointer (S)’s

contents is odd, each of these registers is pushed by the 8 bits. Figure 4.7.3 shows how the registers are

pushed.

In the INTACK sequence, only the contents of the program bank register (PG), program counter (PC), and

processor status register (PS) are pushed onto the stack area. Make sure to push other necessary registers

by software at the beginning of an interrupt routine.

By executing the PSH instruction, all CPU registers other than the stack pointer can be pushed.

4.7 How interrupts are processed

Fig. 4.7.3. How registers are pushed

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