7733 datasheet(91/940 Pages) RENESAS

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7733 Group User's Manual

INTERRUPTS

4–12

Figure 4.5.2 shows the operation of the interrupt priority detection circuit.

The interrupt priority level of a requested interrupt (“Y” in Figure 4.5.2) is compared with the priority level

which is sent from the preceding comparator (“X” in Figure 4.5.2), and then the interrupt with the higher

priority level is sent to the next comparator (“Z” in Figure 4.5.2). (Initial value of “X” is “0.”) For an interrupt

which is not requested, the comparison is not performed and the priority level which is sent from the

preceding comparator is forwarded to the next comparator as it is. After comparison, if the two priority levels

are the same, the priority level which is sent from the preceding comparator is forwarded to the next

comparator. Therefore, if the same priority is set by software, the interrupt priority levels are handled as

follows:

A-D conversion > UART2 transmission/reception > UART1 transmission > UART1 reception > UART0 transmission

> UART0 reception > Timer B2 > Timer B1 > Timer B0 > Timer A4 > Timer A3 > Timer A2 > Timer A1 >

____

Timer A0 > INT2/Key input > INT1 > INT0

By the above comparison, among the multiple interrupt requests which reside at the same sampling timing,

one request with the highest priority level is detected.

And then, the highest priority level detected by the above comparison is compared with the processor

interrupt priority level (IPL). When this interrupt priority level is higher than the processor interrupt priority

level (IPL) and the interrupt disable flag (I) = “0,” the corresponding interrupt request is accepted. An

interrupt request which is not accepted at this time is held until it is accepted or the corresponding interrupt

request bit is cleared to “0” by software (CLB instruction).

The interrupt priority level is detected synchronously with the CPU’s op-code fetch cycle. However, when

an op-code fetch cycle starts during the interrupt priority detection, a new interrupt priority detection does

not start. (Refer to “Figure 4.6.1”) Because the interrupt request bit’s state and interrupt priority level are

latched during interrupt priority detection, if they change, the interrupt priority detection is performed for the

previous state before the change occurred.

4.5 Interrupt priority level detection circuit

Fig. 4.5.2 Interrupt priority level detection model

Comparison

of priority

level

q When X

≥ Y, Z = X

q When X < Y, Z = Y

Interrupt source Y

X : Priority level which is sent from the preceding

comparator (Highest priority at this time)

Y : Priority level of interrupt source Y

Z : Highest priority at this time

Time

Comparator

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