7733 datasheet(681/940 Pages) RENESAS

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CONNECTING EXTERNAL DEVICES

7735 Group User’s Manual

12–5

RSMP

A8/D8 to A15/D15

RSMP

ALE

A8 to A15

D(odd)

ALE

A0/D0 to A7/D7

A8 to A15

A0 to A7

D(even)

A0 to A7

D : Data

ALE

RSMP

E/RDE

RDE

(Note 2)

A8/D8

to A15/D15

P43 to P47

A0/D0

to A7/D7

A8 to A15

A0/D0

to A7/D7

(Note 3)

ALE

HLDA

WEL

HLDA

P43 to P47

A16, A17

CS0 to CS4

(Note 1)

CS0 to CS4

WEL

(Note 2)

WEL

(Note 2)

WEL

HLDA

WEH

(Note 2)

(“H” level output)

WEH

RDY

HOLD

Pin name

16 bits

(BYTE = “L”)

8 bits

(BYTE = “H”)

External data

bus width

Notes 1: When the internal area is accessed, signals CS0 to CS4 are not output. (Output levels are fixed to “H.”)

2: These signals are affected by the signal output disable selection bit (bit 6 at address 6C 16). (Refer to Table

12.1.4.)

3: In the memory expansion mode, this pin functions as a programmable I/O port. Furthermore, it can be

switched to be a clock

output pin when selected by software. In the microprocessor mode, this signal is

affected by the signal output disable selection bit (bit 6 at address 6C 16). (Refer to Table 12.1.3.)

P : Functions as programmable I/O port

D(odd) : Data at odd

address

D(even) : Data at even

address

__ ____

Table 12.1.1 Functions of ports P0 to P4 and pin E/RDE in memory expansion or microprocessor

mode

12.1 Signals required for accessing external devices

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