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7733 Scheda tecnica(PDF) 762 Page - Renesas Technology Corp |
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7733 Scheda tecnica(HTML) 762 Page - Renesas Technology Corp |
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762 / 940 page ![]() MH z] LOW VOLTAGE VERSION 7735 Group User’s Manual 18-14 Fig. 18.6.2 Relationship between tsu(D) and 2 • f(f2) Fig. 18.6.1 Relationship between ta(AD) and 2 • f(f2) 18.6 Applications [ [ns] 2 3 4 5 6 7 8 9 10 11 12 152 0 500 1000 1500 2000 2500 3000 3500 3294 2127 1194 960 794 669 571 430 377 2319 1485 1069 819 652 533 235 1319 569 247 194 69 819 319 119 91 273 494 1544 319 374 444 419 No wait Wait 1 is valid. Wait 0 is valid. External clock input frequency 2 • f(f2) V Address decode time and address latch delay time are not idd [MHz] [ns] 2 3 4 5 6 7 8 9 10 11 12 0 500 1000 1500 2000 208 41 541 875 675 541 1875 1208 319 275 238 875 275 208 160 125 97 75 56 375 446 375 No wait Wait 1 or Wait 0 is valid. External clock input frequency 2•f(f 2) |
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