7733 datasheet(937/940 Pages) RENESAS

937 / 940 page

Rev.

No.

date

2.00

980731

(4)

REVISION DESCRIPTION LIST

7733/7735/7736 Group User’s Manual

Revision Description

Page

PART 1

P7-31

Line 7

PART 1

P8-40

Fig.8.3.13

PART 1

P8-46

Table 8.4.4

PART 1

P8-59

Line 2

PART 1

P8-59

Fig.8.4.11

PART 1

P8-60

Fig. 8.4.12

PART 1

P8-62

Line 20

PART 1

P11-17

Table 11.4.3

14400 f2 52(3F16) 14490.57 53(4016) 14467.59

And then, reception is started when ST is detected.

14400 f2 52(3416) 14490.57 53(3516) 14467.59

And then, the transfer clock is generated when

ST is detected, and reception is started.

CTS

RTSi

CTSi

RTSi

Reception is started at the falling

edge of start bit.

Transfer clock

The transfer clock is generated at the

falling edge of start bit, and reception

is started.

Transfer clock

Interrupt

Conditions for each function which generates interrupt request

when clocks f2 and f512 are

stopped

when clocks f2 and f512 are

not stopped

A-D conversion

interrupt

DisabledEnabled

Interrupt

Conditions for each function which generates interrupt request

when clocks f2 and f512 are

stopped

when clocks f2 and f512 are

not stopped

Disabled

A-D conversion

interrupt

Enabled in one-shot mode and

single sweep mode

CTSi

RTSi

CLK

CLKi

CTSi

RTSi

CLK

CLKi

Revised Version

Previous Version

The timer Bi overflow flag is cleared

to “0” at the next count timing of the

count source when a value is written

to the timer Bi mode register with the

count start flag = “1.”

The timer Bi overflow flag is cleared

to “0” when a value is written to the

timer Bi mode register with the count

start flag = “1.”

For the slave microcomputer whose

address matches bits 6 to 0 in

the receive data, terminate the

sleep mode. (Do not terminate the

sleep mode for the other slave

microcomputers.)

For the slave microcomputer whose

address matches bits 6 to 0 in

the receive data, clear the sleep

mode. (Do not terminate the sleep

mode

for

the

other

slave

microcomputers.)

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