ATtiny13A datasheet(70/174 Pages) ATMEL

70 / 174 page

8126D–AVR–11/09

ATtiny13A

Figure 11-11 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast

PWM mode where OCR0A is TOP.

Figure 11-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-

caler (fclk_I/O/8)

11.9 Register Description

11.9.1

TCCR0A – Timer/Counter Control Register A

• Bits 7:6 – COM01A:0: Compare Match Output A Mode

These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0

bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected

to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin

must be set in order to enable the output driver.

When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the

WGM02:0 bit setting.

Table 11-2 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to a normal or

CTC mode (non-PWM).

OCFnx

OCRnx

TCNTn

(CTC)

TOP

TOP - 1

TOP

BOTTOM

BOTTOM + 1

clk

I/O

clk

(clk

I/O/8)

Bit

210

0x2F

COM0A1

COM0A0

COM0B1

COM0B0

–

WGM01

WGM00

TCCR0A

Read/Write

R/W

Initial Value

Table 11-2.

Compare Output Mode, non-PWM Mode

COM0A1

COM0A0

Description

Normal port operation, OC0A disconnected.

Toggle OC0A on Compare Match

Clear OC0A on Compare Match

Set OC0A on Compare Match

ATtiny13A Scheda tecnica(PDF) 70 Page - ATMEL Corporation

ATtiny13A Scheda tecnica(HTML) 70 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL