ATtiny13A datasheet(46/174 Pages) ATMEL

46 / 174 page

8126D–AVR–11/09

ATtiny13A

9.2

External Interrupts

The External Interrupts are triggered by the INT0 pin or any of the PCINT5..0 pins. Observe that,

if enabled, the interrupts will trigger even if the INT0 or PCINT5..0 pins are configured as out-

puts. This feature provides a way of generating a software interrupt. Pin change interrupts PCI

will trigger if any enabled PCINT5..0 pin toggles. The PCMSK Register control which pins con-

tribute to the pin change interrupts. Pin change interrupts on PCINT5..0 are detected

asynchronously. This implies that these interrupts can be used for waking the part also from

sleep modes other than Idle mode.

The INT0 interrupts can be triggered by a falling or rising edge or a low level. This is set up as

indicated in the specification for the MCU Control Register – MCUCR. When the INT0 interrupt is

enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held

low. Note that recognition of falling or rising edge interrupts on INT0 requires the presence of an

I/O clock, described in “Clock Systems and their Distribution” on page 23.

9.2.1

Low Level Interrupt

A low level interrupt on INT0 is detected asynchronously. This implies that this interrupt can be

used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in

all sleep modes except Idle mode.

Note that if a level triggered interrupt is used for wake-up from Power-down, the required level

must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If

the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter-

rupt will be generated. The start-up time is defined by the SUT and CKSEL fuses as described in

“System Clock and Clock Options” on page 23.

If the low level on the interrupt pin is removed before the device has woken up then program

execution will not be diverted to the interrupt service routine but continue from the instruction fol-

lowing the SLEEP command.

9.2.2

Pin Change Interrupt Timing

An example of timing of a pin change interrupt is shown in Figure 9-1 below.

Figure 9-1.

Timing of pin change interrupts

clk

PCINT(n)

pin_lat

pin_sync

pcint_in_(n)

pcint_syn

pcint_setflag

PCIF

PCINT(0)

pin_sync

pcint_syn

pin_lat

pcint_setflag

PCIF

clk

PCINT(0) in PCMSK(x)

pcint_in_(0)

ATtiny13A Scheda tecnica(PDF) 46 Page - ATMEL Corporation

ATtiny13A Scheda tecnica(HTML) 46 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL