ATtiny13A datasheet(42/174 Pages) ATMEL

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8126D–AVR–11/09

ATtiny13A

8.5

8.5.1

MCUSR – MCU Status Register

The MCU Status Register provides information on which reset source caused an MCU Reset.

• Bits 7:4 – Res: Reserved Bits

These bits are reserved bits in the ATtiny13A and will always read as zero.

• Bit 3 – WDRF: Watchdog Reset Flag

This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 2 – BORF: Brown-out Reset Flag

This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 1 – EXTRF: External Reset Flag

This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 0 – PORF: Power-on Reset Flag

This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.

To make use of the Reset Flags to identify a reset condition, the user should read and then reset

the MCUSR as early as possible in the program. If the register is cleared before another reset

occurs, the source of the reset can be found by examining the Reset Flags.

8.5.2

WDTCR – Watchdog Timer Control Register

• Bit 7 – WDTIF: Watchdog Timer Interrupt Flag

This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is config-

ured for interrupt. WDTIF is cleared by hardware when executing the corresponding interrupt

handling vector. Alternatively, WDTIF is cleared by writing a logic one to the flag. When the I-bit

in SREG and WDTIE are set, the Watchdog Time-out Interrupt is executed.

• Bit 6 – WDTIE: Watchdog Timer Interrupt Enable

When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is

enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt

Mode, and the corresponding interrupt is executed if time-out in the Watchdog Timer occurs.

If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in

the Watchdog Timer will set WDTIF. Executing the corresponding interrupt vector will clear

WDTIE and WDTIF automatically by hardware (the Watchdog goes to System Reset Mode).

Bit

765432

0x34

––––

WDRF

BORF

EXTRF

PORF

MCUSR

Read/Write

RRRR

R/W

Initial Value

0000

See Bit Description

Bit

765

4321

0x21

WDTIF

WDTIE

WDP3

WDCE

WDE

WDP2

WDP1

WDP0

WDTCR

Read/Write

R/W

Initial Value

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