ATtiny13A datasheet(24/174 Pages) ATMEL

24 / 174 page

8126D–AVR–11/09

ATtiny13A

6.1.4

ADC Clock – clkADC

The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks

in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion

results.

6.2

Clock Sources

The device has the following clock source options, selectable by Flash fuse bits as shown

below. The clock from the selected source is input to the AVR clock generator, and routed to the

appropriate modules.

Note:

1. For all fuses “1” means unprogrammed while “0” means programmed.

The various choices for each clocking option is given in the following sections. When the CPU

wakes up from Power-down or Power-save, the selected clock source is used to time the start-

up, ensuring stable Oscillator operation before instruction execution starts. When the CPU starts

from reset, there is an additional delay allowing the power to reach a stable level before com-

mencing normal operation. The Watchdog Oscillator is used for timing this real-time part of the

start-up time. The number of WDT Oscillator cycles used for each time-out is shown in Table 6-

6.2.1

External Clock

To drive the device from an external clock source, CLKI should be driven as shown in Figure 6-

2. To run the device on an external clock, the CKSEL fuses must be programmed to “00”.

Figure 6-2.

External Clock Drive Configuration

Table 6-1.

Device Clocking Options Select

Device Clocking Option

CKSEL1:0(1)

External Clock (see page 24)00

Calibrated Internal 4.8/9.6 MHz Oscillator (see page 25)01, 10

Internal 128 kHz Oscillator (see page 26)11

Table 6-2.

Number of Watchdog Oscillator Cycles

Typ Time-out

Number of Cycles

4 ms

512

64 ms

8K (8,192)

EXTERNAL

CLOCK

SIGNAL

CLKI

GND

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