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AM1808AZCED3 Scheda tecnica(PDF) 30 Page - Texas Instruments

Il numero della parte AM1808AZCED3
Spiegazioni elettronici  AM1808 ARM Microprocessor
PDF  264 Pages
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Produttore elettronici  TI [Texas Instruments]
Homepage  http://www.ti.com
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AM1808AZCED3 Scheda tecnica(HTML) 30 Page - Texas Instruments

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AM1808
SPRS653A – FEBRUARY 2010 – REVISED APRIL 2010
www.ti.com
Table 3-10. Programmable Real-Time Unit (PRU) Terminal Functions (continued)
SIGNAL
POWER
TYPE(1)
PULL(2)
DESCRIPTION
GROUP(3)
NAME
NO.
VP_DIN[7] / UHPI_HD[15] / UPP_D[15] / RMII_TXD[1] /
U18
I
CP[26]
C
PRU0_R31[29]
VP_DIN[6] / UHPI_HD[14] / UPP_D[14] / RMII_TXD[0] /
V16
I
CP[26]
C
PRU0_R31[28]
VP_DIN[5] / UHPI_HD[13] / UPP_D[13] / RMII_TXEN /
R14
I
CP[26]
C
PRU0_R31[27]
VP_DIN[4] / UHPI_HD[12] / UPP_D[12] / RMII_RXD[1] /
W16
I
CP[26]
C
PRU0_R31[26]
VP_DIN[3] / UHPI_HD[11] / UPP_D[11] / RMII_RXD[0] /
V17
I
CP[26]
C
PRU0_R31[25]
VP_DIN[2] / UHPI_HD[10] / UPP_D[10] / RMII_RXER /
W17
I
CP[26]
C
PRU0_R31[24]
VP_DIN[1] / UHPI_HD[9] / UPP_D[9] / RMII_MHZ_50_CLK /
W18
I
CP[26]
C
PRU0_R31[23]
ACLKR / PRU0_R30[20] / GP0[15] / PRU0_R31[22]
A1
I
CP[0]
A
ACLKX / PRU0_R30[19] / GP0[14] / PRU0_R31[21]
B1
I
CP[0]
A
AFSR / GP0[13] / PRU0_R31[20]
C2
I
CP[0]
A
AFSX / GP0[12] / PRU0_R31[19]
B2
I
CP[0]
A
AHCLKR / PRU0_R30[18] / UART1_RTS / GP0[11] / PRU0_R31[18]
A2
I
CP[0]
A
AHCLKX / USB_REFCLKIN / UART1_CTS / GP0[10] /
A3
I
CP[0]
A
PRU0_R31[17]
AMUTE / PRU0_R30[16] / UART2_RTS / GP0[9] / PRU0_R31[16]
D5
I
CP[0]
A
PRU0 Input Signals
VP_DIN[15]_VSYNC / UHPI_HD[7] / UPP_D[7] / PRU0_R30[15] /
V18
I
CP[27]
C
PRU0_R31[15]
VP_DIN[14]_HSYNC / UHPI_HD[6] / UPP_D[6] / PRU0_R30[14] /
V19
I
CP[27]
C
PRU0_R31[14]
VP_DIN[13]_FIELD / UHPI_HD[5] / UPP_D[5] / PRU0_R30[13] /
U19
I
CP[27]
C
PRU0_R31[13]
VP_DIN[12] / UHPI_HD[4] / UPP_D[4] / PRU0_R30[12] /
T16
I
CP[27]
C
PRU0_R31[12]
VP_DIN[11] / UHPI_HD[3] / UPP_D[3] / PRU0_R30[11] /
R18
I
CP[27]
C
PRU0_R31[11]
VP_DIN[10] / UHPI_HD[2] / UPP_D[2] / PRU0_R30[10] /
R19
I
CP[27]
C
PRU0_R31[10]
VP_DIN[9] / UHPI_HD[1] / UPP_D[1] / PRU0_R30[9] / PRU0_R31[9] R15
I
CP[27]
C
AXR8 / CLKS1 / ECAP1_APWM1 / GP0[0] / PRU0_R31[8]
E4
I
CP[3]
A
AXR7 / EPWM1TZ[0] / PRU0_R30[17] / GP1[15] / PRU0_R31[7]
D2
I
CP[4]
A
AXR6 / CLKR0 / GP1[14] / MII_TXEN / PRU0_R31[6]
C1
I
CP[5]
A
EMA_CLK / PRU0_R30[5] / GP2[7] / PRU0_R31[5]
B7
I
CP[16]
B
EMA_SDCKE / PRU0_R30[4] / GP2[6] / PRU0_R31[4]
D8
I
CP[16]
B
EMA_RAS / PRU0_R30[3] / GP2[5] / PRU0_R31[3]
A16
I
CP[16]
B
EMA_CAS / PRU0_R30[2] / GP2[4] / PRU0_R31[2]
A9
I
CP[16]
B
EMA_WAIT[1] / PRU0_R30[1] / GP2[1] / PRU0_R31[1]
B19
I
CP[16]
B
EMA_WAIT[0] / PRU0_R30[0] / GP3[8] / PRU0_R31[0]
B18
I
CP[16]
B
PRU1 Output Signals
30
Device Overview
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