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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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AM1808AZCED3 Scheda tecnica(PDF) 79 Page - Texas Instruments |
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AM1808AZCED3 Scheda tecnica(HTML) 79 Page - Texas Instruments |
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79 / 264 page  AM1808 www.ti.com SPRS653A – FEBRUARY 2010 – REVISED APRIL 2010 The maximum voltage slew rate for CVdd supply changes is 1 mV/us. For additional information on power management solutions from TI for this processor, follow the Power Management link in the Product Folder on www.ti.com for this processor. The processor supports multiple clock domains some of which have clock ratio requirements to each other. PLL0_SYSCLK2:PLL0_SYSCLK4:PLL0_SYSCLK6 are synchronous to each other and the SYSCLKn dividers must always be configured such that the ratio between these domains is 2:4:1. The ASYNC and ASYNC3 clock domains are asynchronous to the other clock domains and have no specific ratio requirement. The table below summarizes the maximum internal clock frequencies at each of the voltage operating points. Table 6-5. Maximum Internal Clock Frequencies at Each Voltage Operating Point CLOCK SOURCE CLOCK DOMAIN 1.3V NOM 1.2V NOM 1.1V NOM 1.0V NOM PLL0_SYSCLK1 Not used on this processor - - - - SYSCLK2 clock domain peripherals and optional PLL0_SYSCLK2 228 MHz 187.5 MHz 100 MHz 50 MHz clock source for ASYNC3 clock domain peripherals PLL0_SYSCLK3 Optional clock for ASYNC1 clock domain 133 MHz 133 MHz 100 MHz 75 MHz PLL0_SYSCLK4 SYSCLK4 domain peripherals 114 MHz 93.75 MHz 50 MHz 25 MHz PLL0_SYSCLK5 Not used on this processor - - - - PLL0_SYSCLK6 ARM subsystem 456 MHz 375 MHz 200 MHz 100 MHz Optional 50 MHz clock source for EMAC RMII PLL0_SYSCLK7 50 MHz 50 MHz - - interface DDR2/mDDR Interface clock source (memory PLL1_SYSCLK1 300 MHz 300 MHz 300 MHz 266 MHz interface clock is one-half of the value shown) Optional clock source for ASYNC3 clock domain PLL1_SYSCLK2 152 MHz 150 MHz 100 MHz 75 MHz peripherals PLL1_SYSCLK3 Alternate clock source input to PLL Controller 0 50 MHz 50 MHz 50 MHz 50 MHz McASP AUXCLK Bypass clock source for the McASP 50 MHz 50 MHz 50 MHz 50 MHz PLL0_AUXCLK Bypass clock source for the USB0 and USB1 48 MHz 48 MHz 48 MHz 48 MHz ASYNC ASYNC Clock Domain (EMIFA) 100 MHz 100 MHz 66.6 MHz 33.3 MHz ASYNC2 ASYNC2 Clock Domain (multiple peripherals) 50 MHz 50 MHz 50 MHz 50 MHz ASYNC3 ASYNC3 Clock Domain (multiple peripherals) 152 MHz 150 MHz 100 MHz 75 MHz Some interfaces have specific limitations on supported modes/speeds at each operating point. See the corresponding peripheral sections of this document for more information. TI provides software components (called the Power Manager) to perform DVFS and abstract the task from the user. The Power Manager controls changing operating points (both frequency and voltage) and handles the related tasks involved such as informing/controlling peripherals to provide graceful transitions between operating points. Copyright © 2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 79 Submit Documentation Feedback Product Folder Link(s): AM1808 |
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