AM1808AZCED3 datasheet(36/264 Pages) TI

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AM1808

SPRS653A – FEBRUARY 2010 – REVISED APRIL 2010

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3.7.12 Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)

Table 3-14. Universal Asynchronous Receiver/Transmitter (UART) Terminal Functions

SIGNAL

POWER

TYPE(1)

PULL(2)

DESCRIPTION

GROUP(3)

NAME

NO.

UART0

SPI0_SCS[5] / UART0_RXD / GP8[4] / MII_RXD[3]

C19

CP[8]

UART0 receive data

SPI0_SCS[4] / UART0_TXD / GP8[3] / MII_RXD[2]

D18

CP[8]

UART0 transmit data

SPI0_SCS[2] / UART0_RTS / GP8[1] / MII_RXD[0] /

D16

CP[9]

UART0 ready-to-send output

SATA_CP_DET

SPI0_SCS[3] / UART0_CTS / GP8[2] / MII_RXD[1] /

E17

CP[9]

UART0 clear-to-send input

SATA_MP_SWITCH

UART1

SPI1_SCS[3] / UART1_RXD / SATA_LED / GP1[1]

E18

CP[13]

UART1 receive data

SPI1_SCS[2] / UART1_TXD / SATA_CP_POD / GP1[0]

F19

CP[13]

UART1 transmit data

AHCLKR / PRU0_R30[18] / UART1_RTS /GP0[11] /

CP[0]

UART1 ready-to-send output

PRU0_R31[18]

AHCLKX / USB_REFCLKIN / UART1_CTS / GP0[10] /

CP[0]

UART1 clear-to-send input

PRU0_R31[17]

UART2

SPI1_SCS[5] / UART2_RXD / I2C1_SCL /GP1[3]

F17

CP[12]

UART2 receive data

SPI1_SCS[4] / UART2_TXD / I2C1_SDA /GP1[2]

F16

CP[12]

UART2 transmit data

AMUTE / PRU0_R30[16] / UART2_RTS / GP0[9] /

CP[0]

UART2 ready-to-send output

PRU0_R31[16]

RTC_ALARM / UART2_CTS / GP0[8] / DEEPSLEEP

CP[0]

UART2 clear-to-send input

(1)

I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name

highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured

function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different

types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.

(2)

IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using

the PUPDENA and PUPDSEL registers in the System Module.The pull-up and pull-down control of these pins is not active until the

device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a

pull-up, an external pull-up can be used.

(3)

This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can

be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of

power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power

supply DVDD3318_C.

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