AM1808AZCED3 datasheet(68/264 Pages) TI

68 / 264 page

AM1808

SPRS653A – FEBRUARY 2010 – REVISED APRIL 2010

www.ti.com

5.3

Electrical Characteristics Over Recommended Ranges of Supply Voltage and

Operating Junction Temperature (Unless Otherwise Noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Low/full speed:

2.8

USB0_VDDA33

USB0_DM and USB0_DP

High speed:

360

440

USB_DM and USB_DP

Low/full speed:

2.8

USB1_VDDA33

VOH

USB1_DM and USB1_DP

DVDD= 3.15V, IOH = -4 mA

2.4

High-level output voltage

(dual-voltage LVCMOS IOs at 3.3V)(1)

DVDD= 3.15V, IOH = -100 mA

2.95

High-level output voltage

DVDD= 1.65V, IOH = -2 mA

DVDD-0.45

(dual-voltage LVCMOS IOs at 1.8V)(1)

Low/full speed:

0.0

0.3

USB_DM and USB_DP

High speed:

-10

USB_DM and USB_DP

VOL

DVDD= 3.15V, IOL = 4mA

0.4

Low-level output voltage

(dual-voltage LVCMOS I/Os at 3.3V)

DVDD= 3.15V, IOL = 100 mA

0.2

Low-level output voltage

DVDD= 1.65V, IOL = 2mA

0.45

(dual-voltage LVCMOS I/Os at 1.8V)

VI = VSS to DVDD without opposing

±9

internal resistor

Input current(1)

VI = VSS to DVDD with opposing

310

(dual-voltage LVCMOS I/Os)

internal pullup resistor (3)

(2)

VI = VSS to DVDD with opposing

-75

-270

internal pulldown resistor (3)

VI = VSS to DVDD with opposing

Input current (DDR2/mDDR I/Os)

-77

-286

internal pulldown resistor (3)

High-level output current(1)

IOH

All peripherals

-6

(dual-voltage LVCMOS I/Os)

Low-level output current(1)

IOL

All peripherals

(dual-voltage LVCMOS I/Os)

Input capacitance (dual-voltage LVCMOS)

Capacit

Output capacitance (dual-voltage

ance

LVCMOS)

(1)

These IO specifications apply to the dual-voltage IOs only and do not apply to the DDR2/mDDR or SATA interfaces. DDR2/mDDR IOs

are 1.8V IOs and adhere to the JESD79-2A standard.

(2)

II applies to input-only pins and bi-directional pins. For input-only pins, II indicates the input leakage current. For bi-directional pins, II

indicates the input leakage current and off-state (Hi-Z) output leakage current.

(3)

Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.

Device Operating Conditions

Submit Documentation Feedback

Product Folder Link(s): AM1808

AM1808AZCED3 Scheda tecnica(PDF) 68 Page - Texas Instruments

AM1808AZCED3 Scheda tecnica(HTML) 68 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL