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AM1808AZCED3 Scheda tecnica(PDF) 51 Page - Texas Instruments

Il numero della parte AM1808AZCED3
Spiegazioni elettronici  AM1808 ARM Microprocessor
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AM1808AZCED3 Scheda tecnica(HTML) 51 Page - Texas Instruments

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AM1808
www.ti.com
SPRS653A – FEBRUARY 2010 – REVISED APRIL 2010
3.7.24
Video Port Interface (VPIF)
Table 3-26. Video Port Interface (VPIF) Terminal Functions
SIGNAL
POWER
TYPE(1)
PULL(2)
DESCRIPTION
GROUP(3)
NAME
NO.
VIDEO INPUT
VP_CLKIN0 / UHPI_HCS / PRU1_R30[10] / GP6[7] /
VPIF capture channel 0
W14
I
CP[25]
C
UPP_2xTXCLK
input clock
VPIF capture channel 1
VP_CLKIN1 / UHPI_HDS1/PRU1_R30[9] / GP6[6] / PRU1_R31[16]
V15
I
CP[25]
C
input clock
VP_DIN[15]_VSYNC / UHPI_HD[7] / UPP_D[7] / PRU0_R30[15] /
V18
I
CP[27]
C
PRU0_R31[15]
VP_DIN[14]_HSYNC / UHPI_HD[6] / UPP_D[6]/ PRU0_R30[14] /
V19
I
CP[27]
C
PRU0_R31[14]
VP_DIN[13]_FIELD / UHPI_HD[5] / UPP_D[5] / PRU0_R30[13] /
U19
I
CP[27]
C
PRU0_R31[13]
VP_DIN[12] / UHPI_HD[4] / UPP_D[4]/ PRU0_R30[12] /
T16
I
CP[27]
C
PRU0_R31[12]
VP_DIN[11] / UHPI_HD[3] / UPP_D[3]/ PRU0_R30[11] /
R18
I
CP[27]
C
PRU0_R31[11]
VP_DIN[10] / UHPI_HD[2] / UPP_D[2] / PRU0_R30[10] /
R19
I
CP[27]
C
PRU0_R31[10]
VP_DIN[9] / UHPI_HD[1] / UPP_D[1] / PRU0_R30[9] /
R15
I
CP[27]
C
PRU0_R31[9]
VP_DIN[8] / UHPI_HD[0] / UPP_D[0] / GP6[5] / PRU1_R31[0]
P17
I
CP[27]
C
VPIF capture data bus
VP_DIN[7] / UHPI_HD[15] / UPP_D[15] / RMII_TXD[1] /
U18
I
CP[26]
C
PRU0_R31[29]
VP_DIN[6] / UHPI_HD[14] / UPP_D[14] / RMII_TXD[0] /
V16
I
CP[26]
C
PRU0_R31[28]
VP_DIN[5] / UHPI_HD[13] / UPP_D[13] / RMII_TXEN /
R14
I
CP[26]
C
PRU0_R31[27]
VP_DIN[4] / UHPI_HD[12] / UPP_D[12] / RMII_RXD[1] /
W16
I
CP[26]
C
PRU0_R31[26]
VP_DIN[3] / UHPI_HD[11] / UPP_D[11] / RMII_RXD[0] /
V17
I
CP[26]
C
PRU0_R31[25]
VP_DIN[2] / UHPI_HD[10] / UPP_D[10] / RMII_RXER /
W17
I
CP[26]
C
PRU0_R31[24]
VP_DIN[1] / UHPI_HD[9] / UPP_D[9] / RMII_MHZ_50_CLK /
W18
I
CP[26]
C
PRU0_R31[23]
VP_DIN[0] / UHPI_HD[8] / UPP_D[8] / RMII_CRS_DV /
W19
I
CP[26]
C
PRU1_R31[29]
VIDEO OUTPUT
VP_CLKIN2 / MMCSD1_DAT[3] / PRU1_R30[3] / GP6[4] /
VPIF display channel 2
H3
I
CP[30]
C
PRU1_R31[4]
input clock
VP_CLKOUT2 / MMCSD1_DAT[2] / PRU1_R30[2] / GP6[3] /
VPIF display channel 2
K3
O
CP[30]
C
PRU1_R31[3]
output clock
(1)
I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2)
IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the
device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a
pull-up, an external pull-up can be used.
(3)
This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power
supply DVDD3318_C.
Copyright © 2010, Texas Instruments Incorporated
Device Overview
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