AM1808AZCED3 datasheet(78/264 Pages) TI

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2000 N

Max PLL Lock Time =

where N = Pre-Divider Ratio

M = PLL Multiplier

AM1808

SPRS653A – FEBRUARY 2010 – REVISED APRIL 2010

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Table 6-4. Allowed PLL Operating Conditions (PLL0 and PLL1)

Default

NO.

PARAMETER

MIN

MAX

UNIT

Value

PLLRST: Assertion time during initialization

N/A

1000

N/A

Lock time: The time that the application has to

wait for the PLL to acquire lock before setting

OSCIN

N/A

PLLEN, after changing PREDIV, PLLM, or

cycles

OSCIN

(1)

PREDIV: Pre-divider value

/32

PLLREF: PLL input frequency

MHz

PLLM: PLL multiplier values

x20

x32

PLLOUT: PLL output frequency

N/A

400

600(1)

MHz

POSTDIV: Post-divider value

/2(1)

/32

(1)

PLL post divider / 2 must be used. The /4.5 clock path can be used to generate an EMIF clock from the undivided (i.e. 600 MHz) PLL

output clock.

6.6.2

Device Clock Generation

PLL0 is controlled by PLL Controller 0 and PLL1 is controlled by PLL Controller 1. PLLC0 and PLLC1

manage the clock ratios, alignment, and gating for the system clocks to the chip. The PLLCs are

responsible for controlling all modes of the PLL through software, in terms of pre-division of the clock

inputs (PLLC0 only), multiply factors within the PLLs, and post-division for each of the chip-level clocks

from the PLLs outputs. PLLC0 also controls reset propagation through the chip, clock alignment, and test

points.

PLLC0 provides clocks for the majority of the system but PLLC1 provides clocks to the mDDR/DDR2

Controller and the ASYNC3 clock domain to provide frequency scaling immunity to a defined set or

peripherals. The ASYNC3 clock domain can either derive its clock from PLL1_SYSCLK2 (for frequency

scaling immunity from PLL0) or from PLL0_SYSCLK2 (for synchronous timing with PLL0) depending on

the application requirements. In addition, some peripherals have specific clock options independent of the

ASYNC clock domain.

6.6.3

Dynamic Voltage and Frequency Scaling (DVFS)

The processor supports multiple operating points by scaling voltage and frequency to minimize power

consumption for a given level of processor performance.

Frequency scaling is achieved by modifying the setting of the PLL controllers’ multipliers, post-dividers

(POSTDIV), and system clock dividers (SYSCLKn). Modification of the POSTDIV and SYSCLK values

does not require relocking the PLL and provides lower latency to switch between operating points, but at

the expense of the frequencies being limited by the integer divide values (only the divide values are

altered the PLL multiplier is left unmodified). Non integer divide frequency values can be achieved by

changing both the multiplier and the divide values, but when the PLL multiplier is changed the PLL must

relock, incurring additional latency to change between operating points. Detailed information on modifying

the PLL Controller settings can be found in SPRUGM9 - AM1808 ARM Microprocessor System Reference

Guide .

Voltage scaling is enabled from outside the device by controlling an external voltage regulator. The

processor may communicate with the regulator using GPIOs, I2C or some other interface. When switching

between voltage-frequency operating points, the voltage must always support the desired frequency.

When moving from a high-performance operating point to a lower performance operating point, the

frequency should be lowered first followed by the voltage. When moving from a low-performance operating

point to a higher performance operating point, the voltage should be raised first followed by the frequency.

Voltage operating points refer to the CVdd voltage at that point. Other static supplies must be maintained

at their nominal voltages at all operating points.

Peripheral Information and Electrical Specifications

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