MC9S08DZ96F2CLL datasheet(39/458 Pages) FREESCALE

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MC9S08DZ128 Series Data Sheet, Rev. 1

Freescale Semiconductor

Chapter 3

Modes of Operation

3.1

Introduction

The operating modes of the MC9S08DZ128 Series are described in this chapter. Entry into each mode,

exit from each mode, and functionality while in each of the modes are described.

3.2

Features

•

Active background mode for code development

•

Wait mode — CPU shuts down to conserve power; system clocks are running and full regulation

is maintained

•

Stop modes — System clocks are stopped and voltage regulator is in standby

— Stop3 — All internal circuits are powered for fast recovery

— Stop2 — Partial power down of internal circuits; RAM content is retained

3.3

Run Mode

This is the normal operating mode for the MC9S08DZ128 Series. This mode is selected when the

BKGD/MS pin is high at the rising edge of reset. In this mode, the CPU executes code from internal

memory with execution beginning at the address fetched from memory at 0xFFFE–0xFFFF after reset.

3.4

Active Background Mode

The active background mode functions are managed through the background debug controller (BDC) in

the HCS08 core. The BDC, together with the on-chip debug module (DBG), provide the means for

analyzing MCU operation during software development.

Active background mode is entered in any of ﬁve ways:

•

When the BKGD/MS pin is low at the rising edge of reset

•

When a BACKGROUND command is received through the BKGD/MS pin

•

When a BGND instruction is executed

•

When encountering a BDC breakpoint

•

When encountering a DBG breakpoint

After entering active background mode, the CPU is held in a suspended state waiting for serial background

commands rather than executing instructions from the user application program.

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