MC9S08DZ96F2CLL datasheet(91/458 Pages) FREESCALE

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Chapter 5 Resets, Interrupts, and General System Control

MC9S08DZ128 Series Data Sheet, Rev. 1

Freescale Semiconductor

5.6

Low-Voltage Detect (LVD) System

The MC9S08DZ128 Series includes a system to protect against low-voltage conditions in order to protect

memory contents and control MCU system states during supply voltage variations. The system is

comprised of a power-on reset (POR) circuit and a LVD circuit with trip voltages for warning and

detection. The LVD circuit is enabled when LVDE in SPMSC1 is set to 1. The LVD is disabled upon

entering any of the stop modes unless LVDSE is set in SPMSC1. If LVDSE and LVDE are both set, then

the MCU cannot enter stop2 (it will enter stop3 instead), and the current consumption in stop3 with the

LVD enabled will be higher.

5.6.1

Power-On Reset Operation

When power is initially applied to the MCU, or when the supply voltage drops below the power-on reset

rearm voltage level, VPOR, the POR circuit will cause a reset condition. As the supply voltage rises, the

LVD circuit will hold the MCU in reset until the supply has risen above the low-voltage detection low

threshold, VLVDL. Both the POR bit and the LVD bit in SRS are set following a POR.

5.6.2

Low-Voltage Detection (LVD) Reset Operation

The LVD can be conﬁgured to generate a reset upon detection of a low-voltage condition by setting

LVDRE to 1. The low-voltage detection threshold is determined by the LVDV bit. After an LVD reset has

occurred, the LVD system will hold the MCU in reset until the supply voltage has risen above the

low-voltage detection threshold. The LVD bit in the SRS register is set following either an LVD reset or

POR.

0xFFF2/0xFFF3

Vtpm1ch1

TPM1

CH1F

CH1IE

TPM1 channel 1

0xFFF4/0xFFF5

Vtpm1ch0

TPM1

CH0F

CH0IE

TPM1 channel 0

0xFFF6/0xFFF7

Vlol

MCG

LOLS

LOLIE

MCG loss of lock

0xFFF8/0xFFF9

Vlvd

System

control

LVWF

LVWIE

Low-voltage warning

0xFFFA/0xFFFB

Virq

IRQ

IRQF

IRQIE

IRQ pin

0xFFFC/0xFFFD

Vswi

Core

SWI Instruction

—

Software interrupt

0xFFFE/0xFFFF

Vreset

System

control

COP,

LOC,

LVD,

RESET,

ILOP,

ILAD,

POR,

BDFR

COPT

CME

LVDRE

—

Watchdog timer

Loss-of-clock

Low-voltage detect

External pin

Illegal opcode

Illegal address

Power-on-reset

BDM-forced reset

1 Vector priority is shown from lowest (ﬁrst row) to highest (last row). For example, Vreset is the highest priority vector.

Table 5-1. Vector Summary1

Vector

Number

Address

(High/Low)

Vector

Name

Module

Source

Enable

Description

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