MC9S08DZ96F2CLL datasheet(68/458 Pages) FREESCALE

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Chapter 4 Memory

MC9S08DZ128 Series Data Sheet, Rev. 1

Freescale Semiconductor

Table 4-12 shows program and erase times. The bus clock frequency and FCDIV determine the frequency

of FCLK (fFCLK). The time for one cycle of FCLK is tFCLK = 1/fFCLK. The times are shown as a number

of cycles of FCLK and as an absolute time for the case where tFCLK =5 μs. Program and erase times

shown include overhead for the command state machine and enabling and disabling of program and erase

voltages.

4.6.3

Program and Erase Command Execution

The FCDIV register must be initialized after any reset and any error ﬂag is cleared before beginning

command execution. The command execution steps are:

1. Write a data value to an address in the FLASH or EEPROM array. The address and data

information from this write is latched into the FLASH and EEPROM interface. This write is a

required ﬁrst step in any command sequence. For erase and blank check commands, the value of

the data is not important. For sector erase commands, the address can be any address in the sector

of FLASH or EEPROM to be erased. For mass erase and blank check commands, the address can

be any address in the FLASH or EEPROM memory. FLASH and EEPROM erase independently

of each other.

NOTE

Before programming a particular byte in the FLASH or EEPROM, the

sector in which that particular byte resides must be erased by a mass or

sector erase operation. Reprogramming bits in an already programmed byte

without ﬁrst performing an erase operation may disturb data stored in the

FLASH or EEPROM memory.

2. Write the command code for the desired command to FCMD. The six valid commands are blank

check (0x05), byte program (0x20), burst program (0x25), sector erase (0x40), mass erase (0x41),

and sector erase abort (0x47). The command code is latched into the command buffer.

3. Write a 1 to the FCBEF bit in FSTAT to clear FCBEF and launch the command (including its

address and data information).

A partial command sequence can be aborted manually by writing a 0 to FCBEF any time after the

write to the memory array and before writing the 1 that clears FCBEF and launches the complete

command. Aborting a command in this way sets the FACCERR access error ﬂag which must be

cleared before starting a new command.

Table 4-12. Program and Erase Times

Parameter

Cycles of FCLK

Time if FCLK = 200 kHz

Byte program

μs

Burst program

μs1

1 Excluding start/end overhead

Sector erase

4000

20 ms

Mass erase

20,000

100 ms

Sector erase abort

μs1

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