MC9S08DZ96F2CLL datasheet(92/458 Pages) FREESCALE

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Chapter 5 Resets, Interrupts, and General System Control

MC9S08DZ128 Series Data Sheet, Rev. 1

Freescale Semiconductor

5.6.3

Low-Voltage Warning (LVW) Interrupt Operation

The LVD system has a low-voltage warning ﬂag to indicate to the user that the supply voltage is

approaching the low-voltage condition. When a low-voltage warning condition is detected and is

conﬁgured for interrupt operation (LVWIE set to 1), LVWF in SPMSC1 will be set and an LVW interrupt

request will occur.

5.7

MCLK Output

The PTA0 pin is shared with the MCLK clock output. If the MCSEL bits are all zeroes, the MCLK clock

is disabled. Setting any of the MCSEL bits causes the PTA0 pin to output a divided version of the internal

MCU bus clock regardless of the state of the port data direction control bit for the pin. The divide ratio is

determined by the MCSEL bits. The slew rate and drive strength for the pin are controlled by PTASE0 and

PTADS0, respectively.

5.8

Reset, Interrupt, and System Control Registers and Control Bits

One 8-bit register in the direct page register space and eight 8-bit registers in the high-page register space

are related to reset and interrupt systems.

Refer to Table 4-2 and Table 4-3 in Chapter 4, “Memory,” of this data sheet for the absolute address

assignments for all registers. This section refers to registers and control bits only by their names. A

Freescale-provided equate or header ﬁle is used to translate these names into the appropriate absolute

addresses.

Some control bits in the SOPT1 and SPMSC2 registers are related to modes of operation. Although brief

descriptions of these bits are provided here, the related functions are discussed in greater detail in

Chapter 3, “Modes of Operation.”

5.8.1

Interrupt Pin Request Status and Control Register (IRQSC)

This direct page register includes status and control bits which are used to conﬁgure the IRQ function,

report status, and acknowledge IRQ events.

76543210

IRQPDD

IRQEDG

IRQPE

IRQF

IRQIE

IRQMOD

IRQACK

Reset

00000000

= Unimplemented or Reserved

Figure 5-2. Interrupt Request Status and Control Register (IRQSC)

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