MC9S08DZ96F2CLL datasheet(97/458 Pages) FREESCALE

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Chapter 5 Resets, Interrupts, and General System Control

MC9S08DZ128 Series Data Sheet, Rev. 1

Freescale Semiconductor

5.8.5

System Options Register 2 (SOPT2)

This high page register contains bits to conﬁgure MCU speciﬁc features on the MC9S08DZ128 Series

devices.

76543210

COPCLKS1

1 This bit can be written only one time after reset. Additional writes are ignored.

COPW1

ADHTS

MCSEL

Reset:

00000000

= Unimplemented or Reserved

Figure 5-6. System Options Register 2 (SOPT2)

Table 5-7. SOPT2 Register Field Descriptions

Field

Description

COPCLKS

COP Watchdog Clock Select — This write-once bit selects the clock source of the COP watchdog. See

Table 5-6 for details.

0 Internal 1-kHz clock is source to COP.

1 Bus clock is source to COP.

COPW

COP Window — This write-once bit selects the COP operation mode. When set, the 0x55-0xAA write sequence

to the SRS register must occur in the last 25% of the selected period. Any write to the SRS register during the

ﬁrst 75% of the selected period will reset the MCU.

0 Normal COP operation.

1 Window COP operation (only if COPCLKS=1).

ADHTS

ADC Hardware Trigger Select — This bit selects which hardware trigger initiates conversion for the analog to

digital converter when the ADC hardware trigger is enabled (ADCTRG is set in ADCSC2 register).

0 Real Time Counter (RTC) overﬂow.

1 External Interrupt Request (IRQ) pin.

2:0

MCSEL

MCLK Divide Select— These bits enable the MCLK output on PTA0 pin and select the divide ratio for the MCLK

output according to the formula below when the MCSEL bits are not equal to all zeroes. In case that the MCSEL

bits are all zeroes, the MCLK output is disabled.

MCLK frequency = Bus Clock frequency

÷ (2 * MCSEL)

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