MC9S08DZ96F2CLL datasheet(63/458 Pages) FREESCALE

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Chapter 4 Memory

MC9S08DZ128 Series Data Sheet, Rev. 1

Freescale Semiconductor

Accessing either the LBP or LWP registers allows a user program to read successive memory locations

without re-writing the linear address pointer. Accessing LBP or LWP does the exact same function.

However, because of the address mapping of the registers with LBP following LWP, a user can do word

accesses in the extended address space using the LDHX or STHX instructions to access location LWP.

The MMU supports the addition of a 2s complement value to the linear address pointer without using any

math instructions or memory resources. Writes to LAPAB with a 2s complement value will cause the

MMU to add that value to the existing value in LAP2:LAP0.

4.4.3

MMU Registers and Control Bits

4.4.3.1

Program Page Register (PPAGE)

The HCS08 Core architecture limits the CPU addressable space available to 64K bytes. The address space

can be extended to 128K bytes using a paging window scheme. The Program Page (PPAGE) allows for

selecting one of the 16K byte blocks to be accessed through the Program Page Window located at

0x8000-0xBFFF. The CALL and RTC instructions can load or store the value of PPAGE onto or from the

stack during program execution. After any reset, PPAGE is set to PAGE 2.

4.4.3.2

Linear Address Pointer Registers 2:0 (LAP2:LAP0)

The three registers, LAP2:LAP0 contain the 17-bit linear address that allows the user to access any FLASH

location in the extended address map. This register is used in conjunction with the data registers, linear

byte (LB), linear byte post increment (LBP) and linear word post increment (LWP). The contents of

LAP2:LAP0 will auto-increment when accessing data using the LBP and LWP registers. The contents of

LAP2:LAP0 can be increased by writing an 8-bit value to LAPAB.

76543210

00000

XA16

XA15

XA14

Reset:

Figure 4-5. Program Page Register (PPAGE)

Table 4-6. Program Page Register Field Descriptions

Field

Description

2:0

XA16:XA14

When the CPU addresses the paging window, 0x8000-0xBFFF, the value in the PPAGE register along with the

CPU addresses A13:A0 are used to create a 17-bit extended address.

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