MC9S08DZ96F2CLL datasheet(76/458 Pages) FREESCALE

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Chapter 4 Memory

MC9S08DZ128 Series Data Sheet, Rev. 1

Freescale Semiconductor

4.6.10

EEPROM Mapping

Only half of the EEPROM is in the memory map. The EPGSEL bit in FCNFG register selects which half

of the array can be accessed in foreground while the other half can not be accessed in background. There

are two mapping mode options that can be selected to conﬁgure the 8-byte EEPROM sectors: 4-byte mode

and 8-byte mode. Each mode is selected by the EPGMOD bit in the FOPT register.

In 4-byte sector mode (EPGMOD = 0), each 8-byte sector splits four bytes on foreground and four bytes

on background but on the same addresses. The EPGSEL bit selects which four bytes can be accessed.

During a sector erase, the entire 8-byte sector (four bytes in foreground and four bytes in background) is

erased.

In 8-byte sector mode (EPGMOD = 1), each entire 8-byte sector is in a single page. The EPGSEL bit

selects which sectors are on background. During a sector erase, the entire 8-byte sector in foreground is

erased.

4.6.11

FLASH and EEPROM Registers and Control Bits

The FLASH and EEPROM modules have seven 8-bit registers in the high-page register space and three

locations in the nonvolatile register space in FLASH memory. Two of those locations are copied into two

corresponding high-page control registers at reset. There is also an 8-byte comparison key in FLASH

memory. Refer to Table 4-3 and Table 4-5 for the absolute address assignments for all FLASH and

EEPROM registers. This section refers to registers and control bits only by their names. A Freescale

Semiconductor-provided equate or header ﬁle normally is used to translate these names into the

appropriate absolute addresses.

4.6.11.1

FLASH and EEPROM Clock Divider Register (FCDIV)

Bit 7 of this register is a read-only status ﬂag. Bits 6 through 0 may be read at any time but can be written

only one time. Before any erase or programming operations are possible, write to this register to set the

frequency of the clock for the nonvolatile memory system within acceptable limits.

76543210

DIVLD

PRDIV8

DIV

Reset

00000000

= Unimplemented or Reserved

Figure 4-14. FLASH and EEPROM Clock Divider Register (FCDIV)

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