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AD1843

C1VID

Clock Generator 1 Video Lock Mode. This bit is used to select between lock modes when the Clock Generator 1 is

referenced to SYNC1 (C1REF set to “1”). This bit should be reset to “0” if C1REF is reset to “0.” When reset to

“0,” Clock Generator 1 is in normal lock mode where the Conversion clock will be frequency and phase locked to

SYNC1, and the Bit clock frequency is chosen using bits C1M7:0 and C1P200. When set to “1,” Clock Generator 1

is in video lock mode, where the Conversion clock frequency is selected using bits C1M7:0, and a Bit clock is not pro-

duced.

C1PLLG

Clock Generator 1 PLL Loop Gain Select. If reset to “0,” this bit selects finite PLL loop gain, and if set to “1,” this

bit selects infinite PLL loop gain. This bit should nominally be reset to “0.” Setting it to “1” may enhance the PLL’s

ability to lock to certain SYNC1 inputs, but it may also increase conversion noise.

C1P200

Clock Generator 1 Bit Clock +200 Frequency Modifier. When set to “1,” the Bit clock driven out of pin BIT1 will

have a frequency that is 200 Hertz greater than the frequency selected through bit C1M7:0. This bit is ignored when

in Video Lock Mode (C1VID set to “1”). C1P200 only modifies the bit clock driven on the BIT1 pin.

C1X8/7

Clock Generator 1 Conversion Clock 8/7 Frequency Modifier. When set to “1,” the Conversion clock frequency gen-

erated will be 8/7 times the value programmed in Control Register Address 17. This bit is ignored when clocks are

referenced to SYNC1 (C1REF set to “1”).

C1C128

Clock Generator 1 Conversion Clock Pin (CONV1) Frequency Select. When set to “1,” the frequency driven on to

the CONV1 pin will be 128 times the conversion rate. When reset to “0,” the frequency driven on to the CONV1 pin

will be the same as the conversion rate. C1C128 only modifies the clock frequency driven on the CONV1 pin.

res

Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.

C1M7:0

Clock Generator 1 Clock Rate Modifiers.

When not in Video Lock Mode (C1REF and C1VID are not both set to “1”):

Bits C1M7:0 select the Bit clock rate which will be driven out on pin BIT1. Using the following table, the least sig-

nificant four bits (C1M3:0) are programmed to the desired Bit clock rate, and the most significant four bits

(C1M7:4) must be programmed to the Conversion clock rate established using Control Register Address 17 and the

C1X8/7 bit. If the actual Conversion clock differs from the value selected by C1M7:4, then the resultant Bit clock

will be different from the rate selected by the ratio of the C1M7:4 selected rate to the Control Register Address 17

plus the C1X8/7 bit actual rate.

C1M3:0

Bit Clock Frequency*

C1M7:4

Conversion (Sample) Rate

0000

2,400

Hertz

0000

7,200

Hertz

0001

4,800

0001

8,400

0010

7,200

0010

9,000

0011

9,600

0011

9,600

0100

12,000

0100

11,200

0101

14,400

0101

12,000

0110

16,800

0110

12,800

0111

19,200

0111

7,200

× 8/7

1000

21,600

1000

9,000

× 8/7

1001

24,000

1001

9,600

× 8/7

1010

26,400

1010

12,000

× 8/7

1011

28,800

1011

Reserved

1100

Reserved

1100

Reserved

1101

Reserved

1101

Reserved

1110

Reserved

1110

Reserved

1111

See Below

1111

See Below

*Bit clock frequencies listed will be increased by 200 Hz if C1P200 is set to “1.”

When C1M7:4 is programmed to “1111” and C1M3:0 is programmed to “1111,” the Bit clock rate will be 128 times

the Conversion rate.

When in Video Lock Mode (C1REF and C1VID are both set to “1”):

Bits C1M7:0 select the Conversion clock rate. The most significant bit (C1M7) must be set to indicate

the type of video lock, either NTSC or PAL. For an NTSC lock, C1M7 must be reset to “0,” and the SYNC1 pin

must receive the NTSC sync frequency (525 lines/frame

× 30 Hz × 1000/1001 frame rate ≈ 15.734 kHz). For a PAL

lock, C1M7 must be set to “1,” and the SYNC1 pin must receive the PAL sync frequency (625 lines/frame

× 25 Hz

frame rate

≈ 15.625 kHz). The next three most significant bits (C1M6:4) select a desired base Conversion clock rate,

and the least significant four bits (C1M3:0) select a divisor. The Conversion clock created by Clock Generator 1 will

be the base divided by the divisor. The following tables list the possible choices for base and divisor.

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