AD1843JS datasheet(34/64 Pages) AD

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REV. 0

–34–

AD1843

LDA1G5:0

Left DAC1 Analog/Digital Gain/Attenuation Select. Least significant bit represents –1.5 dB. Note that the

implementation of the attenuation is mixed analog and digital.

0 00000 =

+12.0 dB:

+12.0 dB Analog,

+0.0 dB Digital

0 01000 =

0.0 dB:

+0.0 dB Analog,

+0.0 dB Digital

0 11111 =

–34.5 dB:

–34.5 dB Analog,

+0.0 dB Digital

1 00000 =

–36.0 dB:

–34.5 dB Analog,

–1.5 dB Digital

1 11111 =

–82.5 dB:

–34.5 dB Analog,

–48.0 dB Digital

RDA1GM

Right DAC1 Analog Mute

0 = Right DAC1 Enabled

1 = Right DAC1 Muted

RDA1G5:0

Right DAC1 Analog/Digital Gain/Attenuation Select. Least significant bit represents –1.5 dB. Note that the

implementation of the attenuation is mixed analog and digital.

0 00000 =

+12.0 dB:

+12.0 dB Analog,

+0.0 dB Digital

0 01000 =

0.0 dB:

+0.0 dB Analog,

+0.0 dB Digital

0 11111 =

–34.5 dB:

–34.5 dB Analog,

+0.0 dB Digital

1 00000 =

–36.0 dB:

–34.5 dB Analog,

–1.5 dB Digital

1 11111 =

–82.5 dB:

–34.5 dB Analog,

–48.0 dB Digital

res

Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.

Initial default state after reset: 1000 1000 1000 1000 (8888 hex). Cleared to default and cannot be written to when:

the RESET pin is asserted LO; when the PWRDWN pin is asserted LO; when the PDNO bit in Control Register

Address 0 is set to “1” (all conversions disabled); when the ANAEN bit in Control Register Address 27 is reset to “0”

(analog channels powered down); or when the DA1EN bit in Control Register Address 27 is reset to “0” (DAC1

disabled).

Address 10

Output Control—DAC2 Analog Gain/Attenuation

Data 15

Data 14

Data 13

Data 12

Data 11

Data 10

Data 9

Data 8

LDA2GM

res

LDA2G5

LDA2G4

LDA2G3

LDA2G2

LDA2G1

LDA2G0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

RDA2GM

res

RDA2G5

RDA2G4

RDA2G3

RDA2G2

RDA2G1

RDA2G0

LDA2GM

Left DAC2 Analog Mute

0 = Left DAC2 Enabled

1 = Left DAC2 Muted

LDA2G5:0

Left DAC2 Analog/Digital Gain/Attenuation Select. Least significant bit represents –1.5 dB. Note that the imple-

mentation of the attenuation is mixed analog and digital.

0 00000 =

+12.0 dB:

+12.0 dB Analog,

+0.0 dB Digital

0 01000 =

0.0 dB:

+0.0 dB Analog,

+0.0 dB Digital

0 11111 =

–34.5 dB:

–34.5 dB Analog,

+0.0 dB Digital

1 00000 =

–36.0 dB:

–34.5 dB Analog,

–1.5 dB Digital

1 11111 =

–82.5 dB:

–34.5 dB Analog,

–48.0 dB Digital

RDA2GM

Right DAC2 Analog Mute

0 = Right DAC2 Enabled

1 = Right DAC2 Muted

RDA2G5:0

Right DAC2 Analog/Digital Gain/Attenuation Select. Least significant bit represents –1.5 dB. Note that the imple-

mentation of the attenuation is mixed analog and digital.

0 00000 =

+12.0 dB:

+12.0 dB Analog,

+0.0 dB Digital

0 01000 =

0.0 dB:

+0.0 dB Analog,

+0.0 dB Digital

0 11111 =

–34.5 dB:

–34.5 dB Analog,

+0.0 dB Digital

1 00000 =

–36.0 dB:

–34.5 dB Analog,

–1.5 dB Digital

1 11111 =

–82.5 dB:

–34.5 dB Analog,

–48.0 dB Digital

res

Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.

Initial default state after reset: 1000 1000 1000 1000 (8888 hex). Cleared to default and cannot be written to when:

the RESET pin is asserted LO; when the PWRDWN pin is asserted LO; when the PDNO bit in Control Register

Address 0 is set to “1” (all conversions disabled); when the ANAEN bit in Control Register Address 27 is reset to “0”

(analog channels powered down); or when the DA2EN bit in Control Register Address 27 is reset to “0” (DAC2

disabled).

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