AD1843JS datasheet(39/64 Pages) AD

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AD1843

REV. 0

–39–

NTSC

(C1M7 = “0”):

Base Frequency In Hz (C1M6:4)

48,000

32,000

44,100

× 2/3

48,000*

44,056

Divisor

(C1M3:0)

(000)

(001)

(010)

(011)

(100)

(101)

(0000)

Yes

(0001)

Yes

(0010)

Yes

(0011)

Yes

(0100)

Yes

(0101)

Yes

(0110)

Yes

(0111)

Yes

*When C1M6:4 = “100,” base frequency is 48,000 Hz only if NTSC sync rate is increased by 1001/1000, or is exactly 15.750 kHz.

PAL

(C1M7 = “1”):

Base Frequency In Hz (C1M6:4)

48,000

32,000

44,100

× 2/3

Divisor

(C1M3:0)

(000)

(001)

(010)

(011)

(0000)

Yes

(0001)

Yes

(0010)

Yes

(0011)

Yes

(0100)

Yes

(0101)

Yes

(0110)

Yes

(0111)

Yes

Initial default state after reset: 0000 0000 1111 1111 (00FF hex). Cleared to default and cannot be written to

when: the RESET pin is asserted LO; or when the PWRDWN pin is asserted LO.

Address 17

Clock Generator 1 Control—Sample Rate

Data 15

Data 14

Data 13

Data 12

Data 11

Data 10

Data 9

Data 8

C1C15

C1C14

C1C13

C1C12

C1C11

C1C10

C1C9

C1C8

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

C1C7

C1C6

C1C5

C1C4

C1C3

C1C2

C1C1

C1C0

C1C15:0

Clock Generator 1 Conversion (Sample) Rate Select. Defines the conversion rate produced by Clock Generator 1

when not referenced to the SYNC1 pin (Control Register Address 16 Bit 15 [C1REF]). One LSB represents exactly

one Hertz, assuming a 24.576 MHz clock input on the XTALI pin. Usable range is 4 kHz (0x0FA0) to 54 kHz

(0xD2F0).

Initial default state after reset: 1011 1011 1000 0000 (BB80 hex), which is 48 kHz, assuming a 24.576 MHz clock in-

put on the XTALI pin. Cleared to default and cannot be written to when: the RESET pin is asserted LO; or when

the PWRDWN pin is asserted LO.

Address 18

Clock Generator 1 Control—Sample Phase Shift

Data 15

Data 14

Data 13

Data 12

Data 11

Data 10

Data 9

Data 8

res

C1PD

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

C1P7

C1P6

C1P5

C1P4

C1P3

C1P2

C1P1

C1P0

C1PD

Clock Generator 1 Phase Shift Direction. This bit controls the direction of sample clock phase shift.

0 = Phase Advance

1 = Phase Retard

C1P7:0

Clock Generator 1 Phase Shift Magnitude. These bits control the magnitude of sample clock phase shift. One LSB

represents exactly 0.12 degrees. LSBs are processed and decremented at a rate of 3.072 MHz (assuming a 24.576

MHz clock input on the XTALI pin). When this register is read, it indicates any phase advance/retard remaining to

be processed as of the beginning of slot 0 if bus master, or when TSI was received if bus slave. This register may be

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