AD1843JS datasheet(15/64 Pages) AD

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AD1843

REV. 0

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lock loops, which can be arbitrarily assigned to the conversion

resources. The lock range of these digital PLLs is 4 kHz to

54 kHz, which is the same range supported by the register-

controlled clock generators.

If a SYNC input stops after its associated phase lock loop has

had a chance to initially lock, the AD1843 will continue to gen-

erate a sample clock (as well as BIT clock and CONV clock)

very similar to the initial frequency, but off by at most

±1%.

The three SYNC inputs feed three on-chip Digital Phase Lock

Loops (DPLLs) which utilize a first-order loop filter with a

20 Hz corner frequency. Jitter frequencies above 20 Hz are

attenuated, and jitter frequencies below 20 Hz are interpreted as

time base drift, and are tracked. The DPLL provides 12 dB per

octave of jitter rejection. The DPLLs have been designed to tol-

erate at least 2% Unit Interval (UI) of SYNC clock jitter. The

DPLLs are critically damped at all input frequencies.

Power Management

The AD1843 SoundComm codec has extensive power manage-

ment capabilities. Hardware power down is performed using the

PWRDWN

pin. Software power management is programmed us-

ing Control Register Address 27 and 28. Several elements of the

AD1843 can be powered down on a selective basis. These blocks

include: the DAC2 to DAC1 analog mixer; the entire DAC1 con-

version channel; the entire DAC2 conversion channel; the analog

half of the ADC, DAC1 and DAC2; the headphone driver; the en-

tire analog mixer; the right ADC channel; the left ADC channel; all

four conversion channels; clock generator 1; clock generator 2;

clock generator 3; conversion clock outputs 1 through 3; bit clock

outputs 1 through 3; and the nominal 24.576 MHz clock output.

Refer to the descriptions of Control Register Address 27 and 28 for

further information.

For proper operation, the AD1843 must be calibrated following

power-up. This initial calibration occurs automatically without any

user intervention or programming. Subsequent to this initial

power-up autocalibration, there is no requirement to recalibrate the

SoundComm codec following software power-down sequences.

The entire AD1843 or selected portions of the device may be

powered down, allowed to idle indefinitely, then powered up

and used immediately, without the need for repeated auto-

calibration. The digital information obtained during the initial

power-up calibration is retained and valid unless the RESET or

PWRDWN

pin is asserted, forcing a hardware reset. (If desired,

the user can specify that a calibration cycle occur when leaving

the software power-down state by setting ACEN (Control Reg-

ister Address 28, Bit 14) to ”1.”) A hardware reset or power-

down clears the calibration information, and therefore a fresh

autocalibration cycle is performed by the AD1843 following this

event. Autocalibration takes approximately 4 ms to complete.

The following table provides an indication of the power savings

associated with powering-down the various resources in the

AD1843. Note that the power savings is somewhat order-

Table I. AD1843 Power-Down Savings

+5 V Digital, +5 V Analog Supplies

Total Active Operation Current: 200 mA

Average, Typical

Absolute IDD +

Normalized

Software Power Down

Control Register Bit(s)

ICC Current

Power Savings

CLKOUT Output

ENCLKO Bit = 0

8 mA

All Bit Clocks and

ENBT3, ENBT2, ENBT1 Bits = 0

All Conversion Clocks

ENCV3, ENCV2, ENCV1 Bits = 0

2 mA

Clock Generator 1

C1EN Bit = 0

6 mA

Clock Generator 2

C2EN Bit = 0

6 mA

Clock Generator 3

C3EN Bit = 0

6 mA

All Clock Generators

C1EN, C2EN, C3EN Bits = 0

20 mA

10%

Headphone Driver

HPEN Bit = 0

8 mA

DAC2 to DAC1 Mix

DDMEN Bit = 0

2 mA

Analog Input to Analog Output Mix

AAMEN Bit = 0

8 mA

ADC Left Channel

ADLEN Bit = 0

8 mA

ADC Right Channel

ADREN Bit = 0

8 mA

ADC Left and Right Channels

ADLEN, ADREN Bits = 0

38 mA

17%

DAC2 (Left and Right Channels)

DA2EN Bit = 0

30 mA

15%

DAC1 (Left and Right Channels)

DA1EN Bit = 0

24 mA

12%

DAC2 AND DAC1 (Left and Right Chs)

DA2EN, DA1EN Bits = 0

60 mA

30%

ADC and DAC2 and DAC1

ADLEN, ADREN,

DA2EN, DA1EN Bits = 0

108 mA

54%

Analog Channel

ANAEN Bit = 0

54 mA

27%

All Control Register 27

HPEN, DDMEN, AAMEN, ADLEN,

ADREN, DA2EN, DA1EN, ANAEN Bits = 0

134 mA

67%

Converter

PDNI Bit = 1

140 mA

70%

All of the Above (Register 27 and

ENCLKO, ENBT3, ENBT2, ENBT1, ENCV3,

Clocks and PDNI)

ENCV2, ENCV1, C1EN, C2EN, C3EN, HPEN,

DDMEN, AAMEN, ADLEN, ADREN, DA2EN,

DA1EN, ANAEN Bits = 0, PDNI Bit = 1

176 mA

88%

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