AD1843JS datasheet(26/64 Pages) AD

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AD1843

CMOUT

VREF

∑

HPOUTR

HPOUTC

HPOUTL

LOUT2LP

LOUT2LN

LOUT2RP

LOUT2RN

LEFT

RIGHT

20 dB

AUX3L

AUX2R

AUX1L

AUX2L

AUX1R

LINRP

LINRN

MICR

MICL

GN/AT = GAIN/

ATTENUATION

DRIVER

AD1843

AAFILTL

AAFILTR

SUML

SUMR

LINLP

LINLN

MOUT

∑

MUTE

∑∆

DAC

MUTE

AUX3R

MIN

∑∆

ADC

PGA

VOLTAGE REFERENCE

CRA2

GN/AT

MUTE

CRA7

GN/AT

MUTE

CRA4

GN/AT

MUTE

CRA5

GN/AT

MUTE

CRA6

GN/AT

MUTE

CRA8

LOUT1L

LOUT1R

GN/AT

MUTE

CRA9

GN/AT

MUTE

CRA3

MUTE

CRA8

GN/AT

MUTE

CRA10

CRAX = CONTROL REGISTER ADDRESS “X”

GNDA

FILTR

FILTL

CRA2

∑∆

DAC

Address

Codec Status and Revision Identification (Read Only)

Channel Status Flags

Input Control—ADC Source and Gain/Attenuation

Mix Control—DAC2 to Mixer

Mix Control—Auxiliary 1 to Mixer

Mix Control—Auxiliary 2 to Mixer

Mix Control—Auxiliary 3 to Mixer

Mix Control—Mic to Mixer

Mix/Misc. Control—Mono In to Mixer and Miscellaneous Settings

Output Control—DAC1 Analog Gain/Attenuation

Output Control—DAC2 Analog Gain/Attenuation

Output Control—DAC1 Digital Attenuation

Output Control—DAC2 Digital Attenuation

Digital Mix Control—ADC to DAC1

Digital Mix Control—ADC to DAC2

Codec Configuration—Channel Sample Rate Source Select

Figure 12. AD1843 Control Registers Associated with Block Diagram

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