AD1843JS datasheet(51/64 Pages) AD

51 / 64 page

AD1843

REV. 0

–51–

Address 30

Reserved for Future Expansion

Data 15

Data 14

Data 13

Data 12

Data 11

Data 10

Data 9

Data 8

res

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

res

Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.

Initial default state after reset: 0000 0000 0000 0000 (0000 hex). Cleared to default and cannot be written to when:

the RESET pin is asserted LO; or when the PWRDWN pin is asserted LO.

Address 31

Reserved for Future Expansion

Data 15

Data 14

Data 13

Data 12

Data 11

Data 10

Data 9

Data 8

res

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

res

Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.

Initial default state after reset: 0000 0000 0000 0000 (0000 hex). Cleared to default and cannot be written to when:

the RESET pin is asserted LO; or when the PWRDWN pin is asserted LO.

BIT AND REGISTER MAPS

A map of all TDM time slot bit assignments and Control Register contents is summarized for reference as follows in Figure 14

and Figure 15:

INPUT SLOT

0 OR 16

1 OR 17

2 OR 18

3 OR 19

4 OR 20

5 OR 21

DATA 15

RES

DATA 15

DATA 14

RES

DATA 14

DATA 13

RES

DATA 13

DATA 12

RES

DATA 12

DATA 11

RES

DATA 11

DATA 10

RES

DATA 10

DATA 9

DA2V

DATA 9

DATA 8

DA1V

DATA 8

DATA 7

R/W

DATA 7

DATA 6

RES

DATA 6

DATA 5

RES

DATA 5

DATA 4

IA4

DATA 4

DATA 3

IA3

DATA 3

DATA 2

IA2

DATA 2

DATA 1

IA1

DATA 1

DATA 0

IA0

DATA 0

OUTPUT SLOT

0 OR 16

1 OR 17

2 OR 18

3 OR 19

4 OR 20

5 OR 21

DATA 15

RES

DATA 15

RES

DATA 14

RES

DATA 14

RES

DATA 13

RES

DATA 13

RES

DATA 12

RES

DATA 12

RES

DATA 11

RES

DATA 11

RES

DATA 10

RES

DATA 10

RES

DATA 9

ADRV

DATA 9

RES

DATA 8

ADLV

DATA 8

RES

DATA 7

RES

DATA 7

RES

DATA 6

RES

DATA 6

RES

DATA 5

RES

DATA 5

RES

DATA 4

RES

DATA 4

RES

DATA 3

RES

DATA 3

RES

DATA 2

RES

DATA 2

RES

DATA 1

DA2RQ

DATA 1

RES

DATA 0

DA1RQ

DATA 0

RES

Figure 14. AD1843 TDM Time Slot Bit Assignment Map

AD1843JS Scheda tecnica(PDF) 51 Page - Analog Devices

AD1843JS Scheda tecnica(HTML) 51 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

Scheda tecnica Scarica

Link URL