AD9914SLASHPCBZ datasheet(34/45 Pages) AD

34 / 45 page

AD9914

Data Sheet

Rev. F | Page 34 of 45

Table 14. Register Map

Name (Serial

Address)

Bit Range

(Parallel

Address)

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

Default

Value

(Hex)1

CFR1—

Control

Function

(0x00)

[7:0]

(0x00)

Digital

power-

down

DAC

power-

down

REF CLK

input

power-

down

Open

External

power-down

control

Open

SDIO input

only

LSB first

mode

0x08

[15:8]

(0x01)

Load LRR

input/

output

update

Autoclear

digital

ramp

accumu-

lator

Autoclear

phase

accumu-

lator

Clear digital

ramp

accumulator

Clear phase

accumulator

Open

External

OSK enable

OSK

enable

0x00

[23:16]

(0x02)

Open

Parallel port

streaming

enable

Enable

sine

output

0x01

[31:24]

(0x03)

Open

VCO cal

enable

0x00

CFR2—

Control

Function

(0x01)

[7:0]

(0x04)

Open

0x00

[15:8]

(0x05)

Matched

latency

enable

Frequency

jump

enable

DRG over

output

enable

Open

SYNC_CLK

enable

SYNC_CLK

invert

Reserved

Open

0x09

[23:16]

(0x06)

Profile

mode

enable

Parallel

data port

enable

Digital ramp destination

Digital ramp

enable

Digital

ramp no-

dwell high

Digital

ramp no-

dwell low

Program

modulus

enable

0x00

[31:24]

(0x07)

Open

0x00

CFR3—

Control

Function

(0x02)

[7:0]

(0x08)

Open

Manual ICP

selection

ICP[2:0]

Lock

detect

enable

Minimum LDW[1:0]

0x1C

[15:8]

(0x09)

Feedback Divider N[7:0]

0x19

[23:16]

(0x0A)

Open

Input

divider

reset

Input divider[1:0]

Doubler

enable

PLL enable

PLL input

divider

enable

Doubler

clock edge

0x00

[31:24]

(0x0B)

Open

0x00

CFR4—

Control

Function

(0x03)

[7:0]

(0x0C)

Requires register default value settings (0x20)

0x20

[15:8]

(0x0D)

Requires register default value settings (0x21)

0x21

[23:16]

(0x0E)

Requires register default value settings (0x05)

0x05

[31:24]

(0x0F)

Open

Auxiliary

divider

power-

down

DAC CAL

clock

power-

down

DAC CAL

enable2

0x00

Digital Ramp

Lower Limit

(0x04)

[7:0]

(0x10)

Digital ramp lower limit[7:0]

0x00

[15:8]

(0x11)

Digital ramp lower limit[15:8]

0x00

[23:16]

(0x12)

Digital ramp lower limit[23:16]

0x00

[31:24]

(0x13)

Digital ramp lower limit[31:24]

0x00

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