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AD9914/PCBZ Scheda tecnica(PDF) 23 Page - Analog Devices |
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AD9914/PCBZ Scheda tecnica(HTML) 23 Page - Analog Devices |
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23 / 45 page  Data Sheet AD9914 Rev. F | Page 23 of 45 DIGITAL RAMP GENERATOR (DRG) DRG Overview To sweep phase, frequency, or amplitude from a defined start point to a defined endpoint, a completely digital ramp generator is included in the AD9914. The DRG makes use of eight control register bits, three external pins, and five 32-bit registers (see Figure 36). DDS CLOCK DIGITAL RAMP ENABLE LOAD LRR AT I/O_UPDATE CLEAR DIGITAL RAMP ACCUMULATOR AUTOCLEAR DIGITAL RAMP ACCUMULATOR 32 32 DIGITAL RAMP DESTINATION 2 DIGITAL RAMP NO-DWELL 2 32 32 63 64 65 32 32 TO DDS SIGNAL CONTROL PARAMETER DIGITAL RAMP GENERATOR DIGITAL RAMP LOWER LIMIT REGISTER RISING DIGITAL RAMP STEP SIZE REGISTER DIGITAL RAMP UPPER LIMIT REGISTER FALLING DIGITAL RAMP STEP SIZE REGISTER DIGITAL RAMP RATE REGISTER Figure 36. Digital Ramp Block Diagram The primary control for the DRG is the digital ramp enable bit (0x01[19]). When disabled, the other DRG input controls are ignored and the internal clocks are shut down to conserve power. The output of the DRG is a 32-bit unsigned data bus that can be routed to any one of the three DDS signal control parameters, as controlled by the two digital ramp destination bits in Control Function Register 2 according to Table 9. The 32-bit output bus is MSB-aligned with the 32-bit frequency parameter, the 16-bit phase parameter, or the 12-bit amplitude parameter, as defined by the destination bits. When the destination is phase or amplitude, the unused LSBs are ignored. Table 9. Digital Ramp Destination Digital Ramp Destination Bits (CFR2[21:20]) DDS Signal Control Parameter Bits Assigned to DDS Parameter 00 Frequency 31:0 01 Phase 31:18 1x1 Amplitude 31:20 1 x = don’t care. The ramp characteristics of the DRG are fully programmable. This includes the upper and lower ramp limits, and independent control of the step size and step rate for both the positive and negative slope characteristics of the ramp. A detailed block diagram of the DRG is shown in Figure 37. The direction of the ramping function is controlled by the DRCTL pin. Logic 0 on this pin causes the DRG to ramp with a negative slope, whereas Logic 1 causes the DRG to ramp with a positive slope. The DRG also supports a hold feature controlled via the DRHOLD pin. When this pin is set to Logic 1, the DRG is stalled at the last state; otherwise, the DRG operates normally. The DDS signal control parameters that are not the destination of the DRG are taken from the active profile. DDS CLOCK D Q R LOWER LIMIT 0 1 DECREMENT STEP SIZE PRESET Q DRCTL LOAD CLEAR DIGITAL RAMP ACCUMULATOR AUTOCLEAR DIGITAL RAMP ACC . NO DWELL LIMIT CONTROL DIGITAL RAMP ACCUMULATOR INCREMENT STEP SIZE 32 32 0 1 NEGATIVE SLOPE RATE POSITIVE SLOPE RATE 16 16 32 16 63 DRHOLD 64 32 32 LOAD CONTROL LOGIC LOAD LRR AT I/O_UPDATE DIGITAL RAMP TIMER ACCUMULATOR RESET CONTROL LOGIC NO-DWELL CONTROL 2 32 32 TO DDS SIGNAL CONTROL PARAMETER UPPER LIMIT 32 Figure 37. Digital Ramp Generator Detail |
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