AD9914SLASHPCBZ datasheet(10/45 Pages) AD

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AD9914

Data Sheet

Rev. F | Page 10 of 45

Pin No.

Mnemonic

I/O1

Description

D8/A0

I/O

Parallel Port Pin/Address Line. The state of the F0 to F3 function pins determines if this pin

acts as a line for direct FSK, PSK, or ASK data or as an address line for programming the

internal registers.

D4/SYNCIO

Parallel Port Pin/Serial Port Synchronization Pin. This pin is D4 for direct FSK, PSK, or ASK data.

If serial mode is invoked via F0 to F3, this pin resets the serial port.

D3/SDO

I/O

Parallel Port Pin/Serial Data Output. This pin is D3 for direct FSK, PSK, or ASK data. If serial

mode is invoked via F0 to F3, this pin is used for readback mode for serial operation.

D2/SDIO/WR

I/O

Parallel Port Pin/Serial Data Input and Output/Write Input. This pin is D2 for direct FSK, PSK, or

ASK data. If serial mode is invoked via F0 to F3, this pin is used for the SDIO for serial operation. If

parallel mode is enabled, this pin is writes to change the values of the internal registers.

D1/SCLK/RD

Parallel Port Pin/Serial Clock/Read Input. This pin is D1 for direct FSK, PSK, or ASK data. If serial

mode is invoked via F0 to F3, this pin is used for SCLK for serial operation. If parallel mode is

enabled, this pin reads back the value of the internal registers.

D0/CS/PWD

Parallel Port Pin/Chip Select/Parallel Width. This pin is D0 for direct FSK, PSK, or ASK data. If

serial mode is invoked via F0 to F3, this pin is used for the chip select for serial operation. If

parallel mode is enabled, this pin sets either 8-bit data or16-bit data.

6, 23, 73

DVDD (1.8V)

Digital Core Supplies (1.8 V).

7, 17, 24, 74, 84

DGND

Digital Ground.

16, 83

DVDD_I/O (3.3V)

Digital Input/Output Supplies (3.3 V).

32, 56, 57

AVDD (1.8V)

Analog Core Supplies (1.8 V).

33, 35, 37, 38,

44, 46, 49, 51

AGND

Analog Ground.

34, 36, 39, 40,

43, 47, 50, 52,

53, 60

AVDD (3.3V)

Analog DAC Supplies (3.3 V).

25, 26, 27

PS0 to PS2

Profile Select Pins. Digital inputs (active high). Use these pins to select one of eight

phase/frequency profiles for the DDS. Changing the state of one of these pins transfers the

current contents of all input/output buffers to the corresponding registers. State changes

must be set up on the SYNC_CLK pin (Pin 82).

28, 29, 30, 31

F0 to F3

Function Pins. Digital inputs. The state of these pins determines if a serial or parallel interface

is used. In addition, the function pins determine how the 32-bit parallel data-word is

partitioned for FSK, PSK, or ASK modulation mode.

AOUT

DAC Complementary Output Source. Analog output (voltage mode). Internally connected

through a 50 Ω resistor to AVDD (3.3 V).

AOUT

DAC Output Source. Analog output (voltage mode). Internally connected through a 50 Ω

resistor to AVDD (3.3 V).

DAC_BP

DAC Bypass Pin. Provides access to the common control node of the DAC current sources.

Connecting a capacitor between this pin and ground can improve noise performance at the

DAC output.

DAC_RSET

Analog Reference. This pin programs the DAC output full-scale reference current. Connect a

3.3 kΩ resistor to AGND.

REF_CLK

Complementary Reference Clock Input. Analog input.

REF_CLK

Reference Clock Input. Analog input.

LOOP_FILTER

External PLL Loop Filter Node.

REF

Local PLL Reference Supply. Typically at 2.05 V.

SYNC_OUT

Digital Synchronization Output. This pin synchronizes multiple chips.

SYNC_IN

Digital Synchronization Input. This pin synchronizes multiple chips.

DRCTL

Ramp Control. Digital input (active high). This pin controls the sweep direction (up/down).

DRHOLD

Ramp Hold. Digital input (active high). Pauses the sweep when active.

DROVER

Ramp Over. Digital output (active high). This pin switches to Logic 1 when the digital ramp

generator reaches the programmed upper or lower limit.

OSK

Output Shift Keying. Digital input (active high). When the OSK features are placed in either

manual or automatic mode, this pin controls the OSK function. In manual mode, it toggles

the multiplier between 0 (low) and the programmed amplitude scale factor (high). In

automatic mode, a low sweeps the amplitude down to zero and a high sweeps the amplitude

up to the amplitude scale factor.

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