AD9914SLASHPCBZ datasheet(18/45 Pages) AD

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AD9914

Data Sheet

Rev. F | Page 18 of 45

When in programmable modulus mode, the 32-bit auxiliary

accumulator operates in a way that allows it to roll over at a

value other than the full capacity of 232. That is, it operates with

a modified modulus based on the programmable value of B.

With each roll over of the auxiliary accumulator, a value of 1

LSB adds to the current accumulated value of the 32-bit phase

accumulator. This behavior changes the modulus of the phase

accumulator to B × 232 (instead of 232), allowing it to synthesize

the desired f0.

To determine the programmable modulus mode register values

for FTW, A, and B, the user must first define f0/fS as a ratio of

relatively prime integers, M/N. That is, having converted f0 and

fS to integers, M and N, reduce the fraction, M/N, to the lowest

terms. Then, divide M × 232 by N. The integer part of this division

operation is the value of FTW (Register 0x04[31:0]). The

remainder, Y, of this division operation is

Y = (232 × M) – (FTW × N)

The value of Y facilitates the determination of A and B by taking

the fraction, Y/N, and reducing it to the lowest terms. Then, the

numerator of the reduced fraction is A (Register 0x06[31:0])

and the denominator is the B (Register 0x05[31:0]).

For example, synthesizing precisely 300 MHz with a 1 GHz

system clock is not possible with a standard DDS. It is possible,

however, using programmable modulus as follows.

First, express f0/fS as a ratio of integers:

300,000,000/1,000,000,000

Reducing this fraction to lowest terms yields 3/10; therefore,

M = 3 and N = 10. FTW is the integer part of (M × 232)/N, or

(3 × 232)/10, which is 1,288,490,188 (0x4CCCCCCC in 32-bit

hexadecimal notation). The remainder, Y, of (3 × 232)/10, is (232

× 3) − (1,288,490,188 × 10), which is 8. Therefore, Y/N is 8/10,

which reduces to 4/5. Therefore, A = 4 and B = 5 (0x00000004

and 0x00000005 in 32-bit hexadecimal notation, respectively).

Programming the AD9914 with these values of FTW, A, and B

results in an output frequency that is exactly 3/10 of the system

clock frequency.

MODE PRIORITY

The ability to activate each mode independently makes it

possible to have multiple data sources attempting to drive the

same DDS signal control parameter (frequency, phase, and

amplitude). To avoid contention, the AD9914 has a built-in

priority system. Table 6 summarizes the priority for each of the

DDS modes. The data source column in Table 6 lists data sources

for a particular DDS signal control parameter in descending

order of precedence. For example, if the profile mode enable bit

and the parallel data port enable bit (0x01[23:22]) are set to

Logic 1 and both are programmed to source the frequency

tuning word to DDS output, the profile modulation mode has

priority over the parallel data port modulation mode.

Table 6. Data Source Priority

Priority

DDS Signal Control Parameters

Data Source

Conditions

Highest Priority

Programmable modulus

If programmable modulus mode is used to output frequency only, no other data source

can control the output frequency in this mode. Note that the DRG is used in conjunction with

programmable modulus mode; therefore, the DRG cannot be used to sweep phase or

amplitude in programmable modulus mode.

If output phase offset control is desired, enable profile mode and use the profile registers

and profile pins accordingly to control output phase adjustment.

If output amplitude control is desired, enable profile mode and use the profile registers

and profile pins accordingly to control output amplitude adjustment. Note that the OSK

enable bit must be set to control the output amplitude.

DRG

The digital ramp modulation mode is the next highest priority mode. If the DRG is

enabled to sweep output frequency, phase, or amplitude, the two parameters not being

swept can be controlled independently via the profile mode.

Profiles

The profile modulation mode is the next highest priority mode. Profile mode can control

all three parameters independently, if desired.

Lowest Priority

Parallel port

Parallel data port modulation has the lowest priority but the most flexibility as far as

changing any parameter at the high rate. See the Programming and Function Pins

section.

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